@Note<74>If the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
<20><><EFBFBD><EFBFBD><EFBFBD>then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Even though the user must manage the cache coherence for read accesses.
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4838 <20>Managing memory protection unit (MPU) in STM32 MCUs<55>
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4839 <20>Level 1 cache on STM32F7 Series<65>
@par Directory contents
- BSP/Src/main.c Main program
- BSP/Src/system_stm32f7xx.c STM32f7xx system clock configuration file
- BSP/Src/stm32f7xx_it.c Interrupt handlers
- BSP/Src/lcd.c LCD drawing features
- BSP/Src/touchscreen.c Touch Screen features
- BSP/Src/log.c LCD Log firmware functions
- BSP/Src/sd.c SD features
- BSP/Src/eeprom.c EEPROM features
- BSP/Src/qspi.c QSPI features
- BSP/Src/audio.c Audio playback features
- BSP/Src/audio_rec_dfsdm.c DFSDM audio record features
- BSP/Inc/main.h Main program header file
- BSP/Inc/stm32f7xx_hal_conf.h HAL configuration file