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/** @page SPI_OneBoard_HalfDuplex_IT SPI example @verbatim ****************************************************************************** * @file Examples_LL/SPI/SPI_OneBoard_HalfDuplex_IT/readme.txt * @author MCD Application Team * @brief Description of the SPI_OneBoard_HalfDuplex_IT example. ****************************************************************************** * @attention * * Copyright (c) 2016 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** @endverbatim @par Example Description Configuration of GPIO and SPI peripherals to transmit bytes from an SPI Master device to an SPI Slave device in Interrupt mode. This example is based on the STM32F7xx SPI LL API. The peripheral initialization uses LL unitary service functions for optimization purposes (performance and size). This example works with only one NUCLEO-F767ZI. SPI1 Peripheral is configured in Master mode Half-Duplex Tx. SPI3 Peripheral is configured in Slave mode Half-Duplex Rx. GPIO associated to User push-button is linked with EXTI. Example execution: LED1 is blinking Fast (200ms) and wait User push-button action. Press User push-button on BOARD start a Half-Duplex communication through IT. On MASTER side (SPI1), Clock will be generated on SCK line, Transmission done on MOSI Line. On SLAVE side (SPI3) reception is done through the MISO Line. LED1 is On if data is well received. In case of errors, LED1 is blinking Slowly (1s). @par Keywords Connectivity, SPI, Full-duplex, Advanced communication, Transmission, Reception, Master, Slave, MISO, MOSI @Note If the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors, then it is highly recommended to enable the CPU cache and maintain its coherence at application level. The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes). @Note It is recommended to enable the cache and maintain its coherence, but depending on the use case It is also possible to configure the MPU as "Write through", to guarantee the write access coherence. In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable. Even though the user must manage the cache coherence for read accesses. Please refer to the AN4838 “Managing memory protection unit (MPU) in STM32 MCUs” Please refer to the AN4839 “Level 1 cache on STM32F7 Series” @par Directory contents - SPI/SPI_OneBoard_HalfDuplex_IT/Inc/stm32f7xx_it.h Interrupt handlers header file - SPI/SPI_OneBoard_HalfDuplex_IT/Inc/main.h Header for main.c module - SPI/SPI_OneBoard_HalfDuplex_IT/Inc/stm32_assert.h Template file to include assert_failed function - SPI/SPI_OneBoard_HalfDuplex_IT/Src/stm32f7xx_it.c Interrupt handlers - SPI/SPI_OneBoard_HalfDuplex_IT/Src/main.c Main program - SPI/SPI_OneBoard_HalfDuplex_IT/Src/system_stm32f7xx.c STM32F7xx system source file @par Hardware and Software environment - This example runs on STM32F767xx devices. - This example has been tested with NUCLEO-F767ZI board and can be easily tailored to any other supported device and development board. - NUCLEO-F767ZI Set-up - Connect Master SCK PA5 to Slave SCK PB3 - Connect Master MOSI PA7 to Slave MISO PB4 Relation with Board connector: PA5 is connected to pin 10 of CN7 connector PA7 is connected to pin 14 of CN7 connector PB3 is connected to pin 15 of CN7 connector PB4 is connected to pin 19 of CN7 connector @par How to use it ? In order to make the program work, you must do the following : - Open your preferred toolchain - Rebuild all files and load your image into target memory - Run the example */