mirror of
https://github.com/STMicroelectronics/STM32CubeF7.git
synced 2025-05-03 22:17:13 +08:00
195 lines
7.9 KiB
C
195 lines
7.9 KiB
C
/**
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******************************************************************************
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* @file QSPI/QSPI_ReadWrite/Inc/main.h
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* @author MCD Application Team
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* @brief Header for main.c module
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2018 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __MAIN_H
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#define __MAIN_H
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f7xx_hal.h"
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#include "stm32f7308_discovery.h"
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/* Exported types ------------------------------------------------------------*/
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/* Exported global variables ---------------------------------------------------*/
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/* Exported constants --------------------------------------------------------*/
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/* Definition for QSPI clock resources */
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#define QSPI_CLK_ENABLE() __HAL_RCC_QSPI_CLK_ENABLE()
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#define QSPI_CLK_DISABLE() __HAL_RCC_QSPI_CLK_DISABLE()
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#define QSPI_CS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
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#define QSPI_CLK_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
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#define QSPI_D0_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
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#define QSPI_D1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
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#define QSPI_D2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOE_CLK_ENABLE()
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#define QSPI_D3_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
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#define QSPI_FORCE_RESET() __HAL_RCC_QSPI_FORCE_RESET()
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#define QSPI_RELEASE_RESET() __HAL_RCC_QSPI_RELEASE_RESET()
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/* Definition for QSPI Pins */
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#define QSPI_CS_PIN GPIO_PIN_6
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#define QSPI_CS_PIN_AF GPIO_AF10_QUADSPI
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#define QSPI_CS_GPIO_PORT GPIOB
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#define QSPI_CLK_PIN GPIO_PIN_2
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#define QSPI_CLK_PIN_AF GPIO_AF9_QUADSPI
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#define QSPI_CLK_GPIO_PORT GPIOB
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#define QSPI_D0_PIN GPIO_PIN_9
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#define QSPI_D0_PIN_AF GPIO_AF9_QUADSPI
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#define QSPI_D0_GPIO_PORT GPIOC
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#define QSPI_D1_PIN GPIO_PIN_10
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#define QSPI_D1_PIN_AF GPIO_AF9_QUADSPI
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#define QSPI_D1_GPIO_PORT GPIOC
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#define QSPI_D2_PIN GPIO_PIN_2
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#define QSPI_D2_PIN_AF GPIO_AF9_QUADSPI
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#define QSPI_D2_GPIO_PORT GPIOE
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#define QSPI_D3_PIN GPIO_PIN_13
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#define QSPI_D3_PIN_AF GPIO_AF9_QUADSPI
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#define QSPI_D3_GPIO_PORT GPIOD
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/* MX25L51245G Macronix memory */
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#define QSPI_FLASH_SIZE 0x4000000 /* 512 MBits => 64MBytes */
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#define QSPI_SECTOR_SIZE 0x10000 /* 1024 sectors of 64KBytes */
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#define QSPI_SUBSECTOR_SIZE 0x1000 /* 16384 subsectors of 4kBytes */
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#define QSPI_PAGE_SIZE 0x100 /* 262144 pages of 256 bytes */
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#define QSPI_DUMMY_CYCLES_READ_QUAD 3
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#define QSPI_DUMMY_CYCLES_READ 8
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#define QSPI_DUMMY_CYCLES_READ_QUAD_IO 10
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#define QSPI_DUMMY_CYCLES_READ_DTR 6
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#define QSPI_DUMMY_CYCLES_READ_QUAD_DTR 8
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#define QSPI_BULK_ERASE_MAX_TIME 600000
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#define QSPI_SECTOR_ERASE_MAX_TIME 2000
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#define QSPI_SUBSECTOR_ERASE_MAX_TIME 800
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/**
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* @brief QSPI Commands
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*/
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/* Reset Operations */
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#define RESET_ENABLE_CMD 0x66
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#define RESET_MEMORY_CMD 0x99
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/* Identification Operations */
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#define READ_ID_CMD 0x9F
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#define MULTIPLE_IO_READ_ID_CMD 0xAF
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#define READ_SERIAL_FLASH_DISCO_PARAM_CMD 0x5A
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/* Read Operations */
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#define READ_CMD 0x03
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#define READ_4_BYTE_ADDR_CMD 0x13
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#define FAST_READ_CMD 0x0B
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#define FAST_READ_DTR_CMD 0x0D
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#define FAST_READ_4_BYTE_ADDR_CMD 0x0C
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#define DUAL_OUT_FAST_READ_CMD 0x3B
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#define DUAL_OUT_FAST_READ_4_BYTE_ADDR_CMD 0x3C
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#define DUAL_INOUT_FAST_READ_CMD 0xBB
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#define DUAL_INOUT_FAST_READ_DTR_CMD 0xBD
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#define DUAL_INOUT_FAST_READ_4_BYTE_ADDR_CMD 0xBC
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#define QUAD_OUT_FAST_READ_CMD 0x6B
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#define QUAD_OUT_FAST_READ_4_BYTE_ADDR_CMD 0x6C
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#define QUAD_INOUT_FAST_READ_CMD 0xEB
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#define QUAD_INOUT_FAST_READ_DTR_CMD 0xED
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#define QPI_READ_4_BYTE_ADDR_CMD 0xEC
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/* Write Operations */
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#define WRITE_ENABLE_CMD 0x06
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#define WRITE_DISABLE_CMD 0x04
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/* Register Operations */
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#define READ_STATUS_REG_CMD 0x05
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#define READ_CFG_REG_CMD 0x15
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#define WRITE_STATUS_CFG_REG_CMD 0x01
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#define READ_LOCK_REG_CMD 0x2D
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#define WRITE_LOCK_REG_CMD 0x2C
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#define READ_EXT_ADDR_REG_CMD 0xC8
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#define WRITE_EXT_ADDR_REG_CMD 0xC5
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/* Program Operations */
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#define PAGE_PROG_CMD 0x02
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#define QPI_PAGE_PROG_4_BYTE_ADDR_CMD 0x12
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#define QUAD_IN_FAST_PROG_CMD 0x38
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#define EXT_QUAD_IN_FAST_PROG_CMD 0x38
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#define QUAD_IN_FAST_PROG_4_BYTE_ADDR_CMD 0x3E
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/* Erase Operations */
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#define SUBSECTOR_ERASE_CMD 0x20
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#define SUBSECTOR_ERASE_4_BYTE_ADDR_CMD 0x21
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#define SECTOR_ERASE_CMD 0xD8
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#define SECTOR_ERASE_4_BYTE_ADDR_CMD 0xDC
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#define BULK_ERASE_CMD 0xC7
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#define PROG_ERASE_RESUME_CMD 0x30
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#define PROG_ERASE_SUSPEND_CMD 0xB0
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/* 4-byte Address Mode Operations */
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#define ENTER_4_BYTE_ADDR_MODE_CMD 0xB7
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#define EXIT_4_BYTE_ADDR_MODE_CMD 0xE9
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/* Quad Operations */
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#define ENTER_QUAD_CMD 0x35
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#define EXIT_QUAD_CMD 0xF5
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/**
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* @brief QSPI Registers
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*/
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/* Status Register */
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#define QSPI_SR_WIP ((uint8_t)0x01) /*!< Write in progress */
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#define QSPI_SR_WREN ((uint8_t)0x02) /*!< Write enable latch */
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#define QSPI_SR_BLOCKPR ((uint8_t)0x5C) /*!< Block protected against program and erase operations */
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#define QSPI_SR_PRBOTTOM ((uint8_t)0x20) /*!< Protected memory area defined by BLOCKPR starts from top or bottom */
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#define QSPI_SR_QUADEN ((uint8_t)0x40) /*!< Quad IO mode enabled if =1 */
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#define QSPI_SR_SRWREN ((uint8_t)0x80) /*!< Status register write enable/disable */
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/* Configuration Register */
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#define QSPI_CR_ODS ((uint8_t)0x07) /*!< Output driver strength */
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#define QSPI_CR_ODS_30 ((uint8_t)0x07) /*!< Output driver strength 30 ohms (default)*/
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#define QSPI_CR_ODS_15 ((uint8_t)0x06) /*!< Output driver strength 15 ohms */
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#define QSPI_CR_ODS_20 ((uint8_t)0x05) /*!< Output driver strength 20 ohms */
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#define QSPI_CR_ODS_45 ((uint8_t)0x03) /*!< Output driver strength 45 ohms */
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#define QSPI_CR_ODS_60 ((uint8_t)0x02) /*!< Output driver strength 60 ohms */
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#define QSPI_CR_ODS_90 ((uint8_t)0x01) /*!< Output driver strength 90 ohms */
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#define QSPI_CR_TB ((uint8_t)0x08) /*!< Top/Bottom bit used to configure the block protect area */
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#define QSPI_CR_PBE ((uint8_t)0x10) /*!< Preamble Bit Enable */
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#define QSPI_CR_4BYTE ((uint8_t)0x20) /*!< 3-bytes or 4-bytes addressing */
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#define QSPI_CR_NB_DUMMY ((uint8_t)0xC0) /*!< Number of dummy clock cycles */
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#define QSPI_MANUFACTURER_ID ((uint8_t)0xC2)
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#define QSPI_DEVICE_ID_MEM_TYPE ((uint8_t)0x20)
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#define QSPI_DEVICE_ID_MEM_CAPACITY ((uint8_t)0x1A)
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#define QSPI_UNIQUE_ID_DATA_LENGTH ((uint8_t)0x10) /*JCC: not checked */
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#endif /* __MAIN_H */
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