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/**
@page TIM_6steps Timers Synchronization example
@verbatim
******************************************************************************
* @file TIM/TIM_6steps/readme.txt
* @author MCD Application Team
* @brief Description of the TIM 6 Steps example.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@endverbatim
@par Example Description
This example shows how to configure the TIM1 peripheral to generate 6 Steps.
The STM32F7xx TIM1 peripheral offers the possibility to program in advance the
configuration for the next TIM1 outputs behaviour (step) and change the configuration
of all the channels at the same time. This operation is possible when the COM
(commutation) event is used.
The COM event can be generated by software by setting the COM bit in the TIM1_EGR
register or by hardware (on TRC rising edge).
In this example, a software COM event is generated each 1 ms: using the SysTick
interrupt.
The TIM1 is configured in Timing Mode, each time a COM event occurs, a new TIM1
configuration will be set in advance. Only changed states are programmed.
The break Polarity is used at High level.
The following Table describes the TIM1 Channels states:
@verbatim
-----------------------------------------------
| Step1 | Step2 | Step3 | Step4 | Step5 | Step6 |
----------------------------------------------------------
|Channel1 | 1(PWM)| 0 | 0 | 0 | 0 |1(PWM) |
----------------------------------------------------------
|Channel1N | 0 | 0 |1(PWM) |1(PWM) | 0 | 0 |
----------------------------------------------------------
|Channel2 | 0 | 0 | 0 |1(PWM) |1(PWM) | 0 |
----------------------------------------------------------
|Channel2N |1(PWM) |1(PWM) | 0 | 0 | 0 | 0 |
----------------------------------------------------------
|Channel3 | 0 |1(PWM) |1(PWM) | 0 | 0 | 0 |
----------------------------------------------------------
|Channel3N | 0 | 0 | 0 | 0 |1(PWM) |1(PWM) |
-----------------------------------------------------------
Channel1 (PA.08) |||||||_________________________________||||||||||||||_________________________________|||||||
Channel1N (PB.13) _______________||||||||||||||||_______________________________||||||||||||||||________________
Channel2 (PA.09) _______________________||||||||||||||||_______________________________||||||||||||||||________
Channel2N (PB.14) |||||||||||||||________________________________|||||||||||||||________________________________
Channel3 (PE.13) _______||||||||||||||||_______________________________||||||||||||||||________________________
Channel3N (PB.15) ________________________________|||||||||||||||________________________________|||||||||||||||
@endverbatim
@par Keywords
Timers, 6 steps, PWM, Duty Cycle, Waveform, Oscilloscope, Output, Signal, commutation, timing mode
@Note<74>If the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
<20><><A0><A0><A0>then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
<0A><><A0><A0><A0><A0>The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
<0A><><A0><A0><A0> It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
<0A><><A0><A0><A0><A0>In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
<0A><><A0><A0><A0><A0>Even though the user must manage the cache coherence for read accesses.
<0A><><A0><A0><A0><A0>Please refer to the AN4838 <20>Managing memory protection unit (MPU) in STM32 MCUs<55>
<0A><><A0><A0><A0><A0>Please refer to the AN4839 <20>Level 1 cache on STM32F7 Series<65>
@par Directory contents
- TIM/TIM_6steps/Inc/stm32f7xx_hal_conf.h HAL configuration file
- TIM/TIM_6steps/Inc/stm32f7xx_it.h Interrupt handlers header file
- TIM/TIM_6steps/Inc/main.h Header for main.c module
- TIM/TIM_6steps/Src/stm32f7xx_it.c Interrupt handlers
- TIM/TIM_6steps/Src/main.c Main program
- TIM/TIM_6steps/Src/stm32f7xx_hal_msp.c HAL MSP file
- TIM/TIM_6steps/Src/system_stm32f7xx.c STM32F7xx system source file
@par Hardware and Software environment
- This example runs on STM32F756xx/STM32F746xx devices.
- This example has been tested with STM327x6G-EVAL board revB and can be
easily tailored to any other supported device and development board.
- STM327x6G-EVAL revB Set-up
Connect the following pins to an oscilloscope to monitor the different waveforms:
- TIM1_CH1 pin (PA.08)
- TIM1_CH1N pin (PB.13)
- TIM1_CH2 pin (PA.09)
- TIM1_CH2N pin (PB.14)
- TIM1_CH3 pin (PE.13)
- TIM1_CH3N pin (PB.15)
- Connect the TIM1 break pin TIM1_BKIN pin (PB.12) to the GND. To generate a
break event, switch this pin level from 0V to 3.3V.
@par How to use it ?
In order to make the program work, you must do the following :
- Open your preferred toolchain
- Rebuild all files: Project->Rebuild all
- Load project image: Project->Download and Debug
- Run program: Debug->Go(F5)
*/