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88 lines
3.9 KiB
Plaintext
88 lines
3.9 KiB
Plaintext
/**
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@page CAN_LoopBack CAN LoopBack example
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@verbatim
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******************************************************************************
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* @file CAN/CAN_LoopBack/readme.txt
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* @author MCD Application Team
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* @brief Description of the CAN LoopBack example.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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@endverbatim
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@par Example Description
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This example shows how to set up a communication with the CAN in loopback mode.
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The CAN cell first performs a transmission and a reception of a standard data
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frame by polling at 1 Mbit/s. The received frame is checked and some LEDs light
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up to indicate whether the communication was successful.
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STM32 Eval board's LEDs can be used to monitor the transfer status:
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- LED1 is ON when the transfer is complete.
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- LED3 is ON when there is a transfer error occurred.
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- LED3 is ON when there is an initialization error occurred.
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@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
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based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
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a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
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than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
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To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
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@note The application need to ensure that the SysTick time base is always set to 1 millisecond
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to have correct HAL operation.
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@par Keywords
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Connectivity, CAN, Communication, Transmission, Reception, Polling,
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@Note If the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
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then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
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The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
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@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
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It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
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In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
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Even though the user must manage the cache coherence for read accesses.
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Please refer to the AN4838 “Managing memory protection unit (MPU) in STM32 MCUs”
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Please refer to the AN4839 “Level 1 cache on STM32F7 Series”
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@par Directory contents
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- CAN/CAN_LoopBack/Inc/stm32f7xx_hal_conf.h HAL configuration file
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- CAN/CAN_LoopBack/Inc/main.h Header for main.c module
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- CAN/CAN_LoopBack/Inc/stm32f7xx_it.h Interrupt handlers header file
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- CAN/CAN_LoopBack/Src/main.c Main program
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- CAN/CAN_LoopBack/Src/stm32f7xx_msp.c HAL MSP module
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- CAN/CAN_LoopBack/Src/stm32f7xx_it.c Interrupt handlers
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- CAN/CAN_LoopBack/Src/system_stm32f7xx.c STM32F7xx system source file
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@par Hardware and Software environment
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- This example runs on STM32F756xx/STM32F746xx devices.
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- This example has been tested with STM32756G-EVAL board and can be
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easily tailored to any other supported device and development board.
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@par How to use it ?
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In order to make the program work, you must do the following :
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- Open your preferred toolchain
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- Rebuild all files and load your image into target memory
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- Run the example
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*/
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