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103 lines
4.9 KiB
Plaintext
103 lines
4.9 KiB
Plaintext
/**
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@page ADC_DualModeInterleaved Use ADC1 and ADC2 in Dual interleaved mode and DMA mode3
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@verbatim
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******************************************************************************
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* @file ADC/ADC_DualModeInterleaved/readme.txt
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* @author MCD Application Team
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* @brief Description of the Dual interleaved mode and DMA mode3 Example
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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@endverbatim
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@par Example Description
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How to use two ADC peripherals to perform conversions in dual interleaved mode.
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The ADC1 and ADC2 are configured to convert ADC_CHANNEL_12, with conversion
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triggered by software.
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The Dual interleaved delay is configured to 6 ADC clk cycles (ADC_TWOSAMPLINGDELAY_6CYCLES).
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On each DMA request (two data items are available) two bytes representing two
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ADC-converted data items are transferred as a half word to uhADCDualConvertedValue variable.
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A DMA request is generated each time 2 data items are available
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1st request: ADC_CDR[15:0] = (ADC2_DR[7:0] << 8) | ADC1_DR[7:0]
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2nd request: ADC_CDR[15:0] = (ADC2_DR[7:0] << 8) | ADC1_DR[7:0]
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The DMA mode 3 is used in interleaved mode in 6-bit and 8-bit resolutions.
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In this example, the system clock is 216MHz, APB2 = 108MHz and ADC clock = APB2/4.
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Since ADCCLK = 27 MHz and Conversion rate = 6 cycles
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==> Conversion Time = 27M/6cyc = 4.5Msps.
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The ADC measure is realized on PC.02, so you need to connect this pin to a power supply (do not forget to connect the power supply
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GND to the EVAL board GND).
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STM32 board's LEDs can be used to monitor the transfer status:
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- LED1 is ON when the conversion is complete.
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- LED3 is ON when there are an error in initialization.
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@note Refer to "simulation.xls" file to have the diagram simulation of the example.
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@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
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based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
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a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
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than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
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To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
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@note The application need to ensure that the SysTick time base is always set to 1 millisecond
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to have correct HAL operation.
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@par Keywords
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Analog, ADC, Analog to Digital, Dual mode, Interleaved, Continuous conversion, Software Trigger, DMA, Measurement,
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@Note<74>If the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
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<20><><EFBFBD><EFBFBD><EFBFBD>then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
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@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Even though the user must manage the cache coherence for read accesses.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4838 <20>Managing memory protection unit (MPU) in STM32 MCUs<55>
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4839 <20>Level 1 cache on STM32F7 Series<65>
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@par Directory contents
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- ADC/ADC_DualModeInterleaved/Inc/stm32f7xx_hal_conf.h HAL configuration file
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- ADC/ADC_DualModeInterleaved/Inc/stm32f7xx_it.h DMA interrupt handlers header file
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- ADC/ADC_DualModeInterleaved/Inc/main.h Header for main.c module
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- ADC/ADC_DualModeInterleaved/Src/stm32f7xx_it.c DMA interrupt handlers
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- ADC/ADC_DualModeInterleaved/Src/main.c Main program
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- ADC/ADC_DualModeInterleaved/Src/stm32f7xx_hal_msp.c HAL MSP file
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- ADC/ADC_DualModeInterleaved/Src/system_stm32f7xx.c STM32F7xx system source file
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@par Hardware and Software environment
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- This example runs on STM32F767xx/STM32F769xx/STM32F777xx/STM32F779xx devices.
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- This example has been tested with STM32769I-EVAL evaluation board and can be
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easily tailored to any other supported device and development board.
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@par How to use it ?
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In order to make the program work, you must do the following :
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- Open your preferred toolchain
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- Rebuild all files and load your image into target memory
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- Run the example
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*/
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