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119 lines
5.7 KiB
Plaintext
119 lines
5.7 KiB
Plaintext
/**
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@page FMC_SDRAM_MemRemap SDRAM memory remap functionnalities example
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@verbatim
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******************************************************************************
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* @file FMC/FMC_SDRAM_MemRemap/readme.txt
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* @author MCD Application Team
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* @brief Description of the FMC SDRAM memory remap example.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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@endverbatim
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@par Example Description
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This example guides you through the different configuration steps to use the IS42S32800G
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SDRAM memory (mounted on STM327x6G-EVAL revB evaluation board) as code execution memory.
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In addition, in this example, the SDRAM is used as data memory.
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A swap between the FMC SDRAM banks and FMC NOR/PSRAM is implemented in order to enable
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the code execution from SDRAM Banks without modifying the default MPU attribute.
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At the beginning of the main program the HAL_Init() function is called to reset
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all the peripherals, initialize the Flash interface and the systick.
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Then the SystemClock_Config() function is used to configure the system
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clock (SYSCLK) to run at 200 MHz.
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The example scenario does not reflect a real application case, its purpose is to
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provide only the procedure to follow to use the external SDRAM as data & execution memory.
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This example does not use the default library startup file. It uses a modified
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startup file provided with the example. While startup, the SDRAM memory is configured
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and initialized to be ready to contain data.
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The user has to configure his preferred toolchain using the provided linker file.
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The RAM zone is modified in order to use the external SDRAM memory as a RAM.
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In addition, in the linker file, a new memory section ".sdram" is added, where code
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can be executed.
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At this stage, all the used data can be located in the external SRAM memory.
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In addition, a pragma instruction is used for SystemClock_Config() function to be executed on SDRAM.
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The user can use the debugger's watch to evaluate "uwTabAddr" and "MSPValue" variables
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values which should be above 0x60000000 (SDRAM offset after implementing memory mapping swap).
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Eval board's LEDs can be used to monitor the example status:
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1. Check SDRAM as Data Memory:
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If uwTabAddr and MSPValue values are in the external SDRAM memory, LED1 is ON, otherwise the LED3 is toggling.
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2. Check SDRAM as Execution Memory:
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LED3 is ON when executing the SystemClock_Config function from SDRAM.
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@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
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based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
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a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
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than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
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To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
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@note The application need to ensure that the SysTick time base is always set to 1 millisecond
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to have correct HAL operation.
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@note The STM32F7xx devices can reach a maximum clock frequency of 216MHz but as this example uses SDRAM,
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the system clock is limited to 200MHz. Indeed proper functioning of the SDRAM is only guaranteed
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at a maximum system clock frequency of 200MHz.
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@par Keywords
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Memory, FMC, SDRAM, Read, Write, Initialization, Access, Memory remap, Code execution, NOR, PSRAM,
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@Note<74>If the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
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<20><><EFBFBD><EFBFBD><EFBFBD>then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
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@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Even though the user must manage the cache coherence for read accesses.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4838 <20>Managing memory protection unit (MPU) in STM32 MCUs<55>
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4839 <20>Level 1 cache on STM32F7 Series<65>
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@par Directory contents
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- FMC/FMC_SDRAM_MemRemap/Inc/stm32f7xx_hal_conf.h HAL configuration file
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- FMC/FMC_SDRAM_MemRemap/Inc/main.h Header for main.c module
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- FMC/FMC_SDRAM_MemRemap/Inc/stm32f7xx_it.h Interrupt handlers header file
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- FMC/FMC_SDRAM_MemRemap/Src/main.c Main program
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- FMC/FMC_SDRAM_MemRemap/Src/stm32f7xx_it.c Interrupt handlers
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- FMC/FMC_SDRAM_MemRemap/Src/system_stm32f7xx.c STM32F7xx system source file
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@par Hardware and Software environment
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- This example runs on STM32F756xx/STM32F746xx devices.
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- This example has been tested with STM327x6G-EVAL board revB and can be
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easily tailored to any other supported device and development board.
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- To use LED1, please ensure that JP24 is set in 2-3 position.
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- To use LED3, please ensure that JP23 is set in 2-3 position.
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@par How to use it ?
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In order to make the program work, you must do the following :
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- Open your preferred toolchain
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- Rebuild all files and load your image into target memory
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- Run the example
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*/
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