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117 lines
5.5 KiB
Plaintext
117 lines
5.5 KiB
Plaintext
/**
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@page TIM_OnePulse TIM example
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@verbatim
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******************************************************************************
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* @file Examples_LL/TIM/TIM_OnePulse/readme.txt
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* @author MCD Application Team
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* @brief Description of the TIM_OnePulse example.
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******************************************************************************
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*
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* Copyright (c) 2016 STMicroelectronics. All rights reserved.
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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@endverbatim
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@par Example Description
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Configuration of a timer to generate a positive pulse in
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Output Compare mode with a length of tPULSE and after a delay of tDELAY. This example
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is based on the STM32F7xx TIM LL API. The peripheral initialization uses
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LL unitary service functions for optimization purposes (performance and size).
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The pulse is generated on OC3.
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This example uses 2 timer instances:
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- TIM1 generates a positive pulse of 50 us after a delay of 50 us. User push-button
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is used to start TIM1 counter.
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___
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User push-button ________________________| |________________________________
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___________
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OC1 ______________________________________| |________
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(TIM1_CH1) <---50 us---><---50 us--->
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| |_ uwMeasuredPulseLength
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|_ uwMeasuredDelay
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TIM1_CH1 delay and pulse length are measured every time a pulse is generated.
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Both can be observed through the debugger by monitoring the variables uwMeasuredDelay and
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uwMeasuredPulseLength respectively.
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- TIM3 generates a positive pulse of 3 s after a delay of 2 s. TIM3 counter start
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is controlled through the slave mode controller. TI2FP2 signals is selected as
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trigger input meaning that TIM3 counter starts when a rising edge is detected on
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TI2FP2. The TIM3 output channel is mapped on the pin PB.0 (connected to LED1 on board
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NUCLEO-F767ZI). Thus LED1 status (on/off) mirrors the timer output level (active v.s. inactive).
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___
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TI2 _________________________| |_________________________________________
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(TIM3_CH2)
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___________________________
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OC3 ______________________________________| |____
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(TIM3_CH3) <-----2s-----><----------3 s------------->
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Both TIM1 and TIM3 are configured to generate a single pulse (timer counter
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stops automatically at the next update event (UEV).
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Connecting TIM1 OC1 to TIM3 TI2 allows to trigger TIM3 counter by pressing
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the User push-button.
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@par Keywords
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Timers, Output, signals, One Pulse, PWM, Oscilloscope, External signal, Autoreload, Waveform
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@Note<74>If the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
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<20><><EFBFBD><EFBFBD><EFBFBD>then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
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@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Even though the user must manage the cache coherence for read accesses.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4838 <20>Managing memory protection unit (MPU) in STM32 MCUs<55>
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4839 <20>Level 1 cache on STM32F7 Series<65>
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@par Directory contents
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- TIM/TIM_OnePulse/Inc/stm32f7xx_it.h Interrupt handlers header file
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- TIM/TIM_OnePulse/Inc/main.h Header for main.c module
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- TIM/TIM_OnePulse/Inc/stm32_assert.h Template file to include assert_failed function
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- TIM/TIM_OnePulse/Src/stm32f7xx_it.c Interrupt handlers
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- TIM/TIM_OnePulse/Src/main.c Main program
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- TIM/TIM_OnePulse/Src/system_stm32f7xx.c STM32F7xx system source file
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@par Hardware and Software environment
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- This example runs on STM32F767xx devices.
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- This example has been tested with NUCLEO-F767ZI board and can be
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easily tailored to any other supported device and development board.
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- NUCLEO-F767ZI Set-up:
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- TIM1_CH1 PE.09: connected to pin 4 of CN10 connector
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- TIM3_CH3 PB.00: connected to pin 31 of CN10 connector
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- TIM3_CH2 PB.05: connected to pin 13 of CN7 connector
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@par How to use it ?
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In order to make the program work, you must do the following :
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- Open your preferred toolchain
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- Rebuild all files and load your image into target memory
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- Run the example
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* <h3><center>© COPYRIGHT STMicroelectronics</center></h3>
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*/
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