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88 lines
3.9 KiB
Plaintext
88 lines
3.9 KiB
Plaintext
/**
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@page GPIO_EXTI GPIO EXTI example
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@verbatim
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******************************************************************************
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* @file GPIO/GPIO_EXTI/readme.txt
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* @author MCD Application Team
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* @brief Description of the GPIO EXTI example.
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******************************************************************************
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*
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* Copyright (c) 2016 STMicroelectronics. All rights reserved.
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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@endverbatim
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@par Example Description
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How to configure external interrupt lines.
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In this example, one EXTI line (EXTI_Line15_10) is configured to generate
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an interrupt on each rising edge.
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In the interrupt routine a led connected to a specific GPIO pin is toggled.
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In this example:
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- EXTI_Line15_10 is connected to PC.13 pin
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- when falling edge is detected on EXTI_Line15_10 by pressing User push-button, LED1 toggles once
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On STM32F767ZI-Nucleo:
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- EXTI_Line15_10 is connected to User push-button
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In this example, HCLK is configured at 216 MHz.
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@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
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based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
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a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
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than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
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To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
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@note The application need to ensure that the SysTick time base is always set to 1 millisecond
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to have correct HAL operation.
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@par Keywords
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System, GPIO, Output, Alternate function, EXTI, Toggle
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@Note If the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
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then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
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The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
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@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
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It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
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In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
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Even though the user must manage the cache coherence for read accesses.
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Please refer to the AN4838 “Managing memory protection unit (MPU) in STM32 MCUs”
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Please refer to the AN4839 “Level 1 cache on STM32F7 Series”
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@par Directory contents
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- GPIO/GPIO_EXTI/Inc/stm32f7xx_hal_conf.h HAL configuration file
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- GPIO/GPIO_EXTI/Inc/stm32f7xx_it.h Interrupt handlers header file
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- GPIO/GPIO_EXTI/Inc/main.h Header for main.c module
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- GPIO/GPIO_EXTI/Src/stm32f7xx_it.c Interrupt handlers
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- GPIO/GPIO_EXTI/Src/main.c Main program
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- GPIO/GPIO_EXTI/Src/system_stm32f7xx.c STM32F7xx system source file
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@par Hardware and Software environment
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- This example runs on STM32F767ZI devices.
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- This example has been tested with STM32F767ZI-Nucleo board and can be
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easily tailored to any other supported device and development board.
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@par How to use it ?
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In order to make the program work, you must do the following :
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- Open your preferred toolchain
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- Rebuild all files and load your image into target memory
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- Run the example
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* <h3><center>© COPYRIGHT STMicroelectronics</center></h3>
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*/
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