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116 lines
4.8 KiB
Plaintext
116 lines
4.8 KiB
Plaintext
/**
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@page UART_Printf UART Printf example
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@verbatim
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******************************************************************************
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* @file UART/UART_Printf/readme.txt
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* @author MCD Application Team
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* @brief Description of the UART Hyperterminal example.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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@endverbatim
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@par Example Description
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Re-routing of the C library printf function to the UART.
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The UART outputs a message on the HyperTerminal.
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The USART is configured as follows:
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- BaudRate = 9600 baud
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- Word Length = 8 Bits (7 data bit + 1 parity bit)
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- One Stop Bit
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- Odd parity
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- Hardware flow control disabled (RTS and CTS signals)
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- Reception and transmission are enabled in the time
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@note USARTx/UARTx instance used and associated resources can be updated in "main.h"
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file depending hardware configuration used.
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@note When the parity is enabled, the computed parity is inserted at the MSB
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position of the transmitted data.
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Board: STM327x6G-EVAL revB
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Tx Pin: PA.09
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Rx Pin: PA.10
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_________________________
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| ______________| _______________
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| |USART | | HyperTerminal |
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| | TX |______________________|RX |
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| | | RS232 Cable | |
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| | RX |______________________|TX |
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| |______________| |_______________|
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|_STM32_Board_____________|
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@par Keywords
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Connectivity, UART, Printf, Baud rate, RS-232, HyperTerminal, full-duplex
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@Note<74>If the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
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<20><><EFBFBD><EFBFBD><EFBFBD>then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
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@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Even though the user must manage the cache coherence for read accesses.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4838 <20>Managing memory protection unit (MPU) in STM32 MCUs<55>
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4839 <20>Level 1 cache on STM32F7 Series<65>
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@par Directory contents
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- UART/UART_Printf/Inc/stm32f7xx_hal_conf.h HAL configuration file
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- UART/UART_Printf/Inc/stm32f7xx_it.h Interrupt handlers header file
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- UART/UART_Printf/Inc/main.h Header for main.c module
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- UART/UART_Printf/Src/stm32f7xx_it.c Interrupt handlers
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- UART/UART_Printf/Src/main.c Main program
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- UART/UART_Printf/Src/stm32f7xx_hal_msp.c HAL MSP module
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- UART/UART_Printf/Src/system_stm32f7xx.c STM32F7xx system source file
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@par Hardware and Software environment
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- This example runs on STM32F756xx/STM32F746xx devices.
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- This example has been tested with STM327x6G-EVAL board revB and can be
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easily tailored to any other supported device and development board.
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- STM32756G_EVAL Set-up
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- Connect a null-modem female/female RS232 cable between the DB9 connector
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CN7 (USART1) and PC serial port if you want to display data on the HyperTerminal.
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@note Make sure that jumper JP7 is on RS232_RX position.
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- Hyperterminal configuration:
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- Word Length = 7 Bits
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- One Stop Bit
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- Odd parity
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- BaudRate = 9600 baud
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- flow control: None
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@par How to use it ?
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In order to make the program work, you must do the following :
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- Open your preferred toolchain
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- Rebuild all files and load your image into target memory
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- Run the example
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*/
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