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110 lines
5.3 KiB
Plaintext
110 lines
5.3 KiB
Plaintext
/**
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@page DMA2D_RegToMemWithLCD DMA2D Register to Memory with LCD example
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@verbatim
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******************************************************************************
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* @file DMA2D/DMA2D_RegToMemWithLCD/readme.txt
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* @author MCD Application Team
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* @brief Description of the DMA2D Register to Memory with LCD example.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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@endverbatim
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@par Example Description
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How to configure DMA2D peripheral in Register-to-memory transfer mode and
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display the result on the LCD.
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The register to Memory mode of the DMA2D is used to copy a fixed color in format ARGB4444 (16 bpp).
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The fixed color value used is 0xF0FF. It is copied from register to a SRAM memory area aBufferResult[]
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of 100x100 pixels in same format ARGB4444 which is filled by the DMA2D with fixed pattern ARGB4444 0xF0FF.
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The LTDC is then used to display the aBufferResult[] which is a 100x100 ARGB4444 fixed color image on LCD.
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At the beginning of the main program the HAL_Init() function is called to reset
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all the peripherals, initialize the Flash interface and the systick.
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Then the SystemClock_Config() function is used to configure the system
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clock (SYSCLK) to run at 216 MHz.
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The Register_to_Memory transfer mode, is used to fill a user defined area by a
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fixed color.
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After DMA2D configuration, the data transfer is performed and then the LCD is
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configured to display color zone created after this transfer on LCD.
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(more details about LCD configuration in LCD examples)
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@note
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=> Output offset is the number of pixel to be skipped after each transferred line
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how to calculate the size of the transferred data ?
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=> selected color mode gives the number of bits per pixel and we have
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(ARGB4444 => 16bits/pixel) the number of pixel per line and the number of line,
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therefore :
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data_size = (bits per pixel) X (pixel per line + output offset) X (number of line)
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STM327x6G-EVAL board revB's LEDs can be used to monitor the transfer status:
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- LED1 is ON when the DMA2D transfer is complete.
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- LED2 is ON when there is a DMA2D transfer error.
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- LED3 is ON when there is an error in LTDC transfer/Init process.
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@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
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based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
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a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
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than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
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To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
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@note The application need to ensure that the SysTick time base is always set to 1 millisecond
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to have correct HAL operation.
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@par Keywords
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Display, Graphic, DMA2D, LCD, ARGB4444, Blending, Register to memory, LTDC, Pixel
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@Note<74>If the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
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<20><><EFBFBD><EFBFBD><EFBFBD>then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
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@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Even though the user must manage the cache coherence for read accesses.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4838 <20>Managing memory protection unit (MPU) in STM32 MCUs<55>
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4839 <20>Level 1 cache on STM32F7 Series<65>
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@par Directory contents
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- DMA2D/DMA2D_RegToMemWithLCD/Inc/main.h Main configuration file
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- DMA2D/DMA2D_RegToMemWithLCD/Inc/stm32f7xx_it.h Interrupt handlers header file
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- DMA2D/DMA2D_RegToMemWithLCD/Inc/stm32f7xx_hal_conf.h HAL configuration file
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- DMA2D/DMA2D_RegToMemWithLCD/Src/main.c Main program
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- DMA2D/DMA2D_RegToMemWithLCD/Src/stm32f7xx_it.c Interrupt handlers
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- DMA2D/DMA2D_RegToMemWithLCD/Src/stm32f7xx_hal_msp.c HAL MSP module
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- DMA2D/DMA2D_RegToMemWithLCD/Src/system_stm32f7xx.c STM32F7xx system clock configuration file
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@par Hardware and Software environment
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- This example runs on STM32F756xx/STM32F746xx devices.
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- This example has been tested with STM327x6G-EVAL board revBs and can be easily
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tailored to any other supported device and development board.
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@par How to use it ?
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In order to make the program work, you must do the following :
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- Open your preferred toolchain
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- Rebuild all files and load your image into target memory
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- Run the example
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*/
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