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/** @page RNG_GenerateRandomNumbers_IT RNG : Random Number Generation using IT @verbatim ****************************************************************************** * @file Examples_LL/RNG/RNG_GenerateRandomNumbers_IT/readme.txt * @author MCD Application Team * @brief Description of the RNG_GenerateRandomNumbers_IT example. ****************************************************************************** * @attention * * Copyright (c) 2016 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** @endverbatim @par Example Description Configuration of the RNG to generate 32-bit long random numbers using interrupts. The peripheral initialization uses LL unitary service functions for optimization purposes (performance and size). Example execution: After startup from reset and system configuration, RNG configuration is performed. (Configure PLLSA11 to enable 48M domain, then enable PLLSAI1 output mapped on 48MHz domain clock and configure PLLSAI as RNG clock source). User is then asked to press key button (LED1 blinking fast). On user button press, several (8) Random 32bit numbers are generated (On each raised RNG interrupt, a random number is generated and retrieved from DR register). Corresponding generated values are available and stored in a u32 array (aRandom32bit), whose content could be displayed using debugger (Watch or LiveWatch features). After successful Random numbers generation, LED1 is turned On. In case of errors, LED1 is slowly blinking (1sec period). @par Keywords Analog, RNG, Random, FIPS PUB 140-2, Analog Random number generator, Entropy, Period, Interrupt @Note If the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors, then it is highly recommended to enable the CPU cache and maintain its coherence at application level. The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes). @Note It is recommended to enable the cache and maintain its coherence, but depending on the use case It is also possible to configure the MPU as "Write through", to guarantee the write access coherence. In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable. Even though the user must manage the cache coherence for read accesses. Please refer to the AN4838 “Managing memory protection unit (MPU) in STM32 MCUs” Please refer to the AN4839 “Level 1 cache on STM32F7 Series” @par Directory contents - RNG/RNG_GenerateRandomNumbers_IT/Inc/stm32f7xx_it.h Interrupt handlers header file - RNG/RNG_GenerateRandomNumbers_IT/Inc/main.h Header for main.c module - RNG/RNG_GenerateRandomNumbers_IT/Inc/stm32_assert.h Template file to include assert_failed function - RNG/RNG_GenerateRandomNumbers_IT/Src/stm32f7xx_it.c Interrupt handlers - RNG/RNG_GenerateRandomNumbers_IT/Src/main.c Main program - RNG/RNG_GenerateRandomNumbers_IT/Src/system_stm32f7xx.c STM32F7xx system source file @par Hardware and Software environment - This example runs on STM32F767xx devices. - This example has been tested with NUCLEO-F767ZI board and can be easily tailored to any other supported device and development board. @par How to use it ? In order to make the program work, you must do the following : - Open your preferred toolchain - Rebuild all files and load your image into target memory - Run the example - Push User button and use Variable watch window from debugger to access to values of generated numbers. (A break point could be set on LED_On() call, at end of RandomNumbersGeneration_IT() function). */