mirror of
https://github.com/STMicroelectronics/STM32CubeF7.git
synced 2025-05-01 22:18:34 +08:00
/** @page UART_Printf UART Printf example @verbatim ****************************************************************************** * @file UART/UART_Printf/readme.txt * @author MCD Application Team * @brief Description of the UART Hyperterminal example. ****************************************************************************** * @attention * * Copyright (c) 2016 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** @endverbatim @par Example Description Re-routing of the C library printf function to the UART. The UART outputs a message on the HyperTerminal. The USART is configured as follows: - BaudRate = 9600 baud - Word Length = 8 Bits (7 data bit + 1 parity bit) - One Stop Bit - Odd parity - Hardware flow control disabled (RTS and CTS signals) - Reception and transmission are enabled in the time @note USARTx/UARTx instance used and associated resources can be updated in "main.h" file depending hardware configuration used. @note When the parity is enabled, the computed parity is inserted at the MSB position of the transmitted data. Board: STM327x6G-EVAL revB Tx Pin: PA.09 Rx Pin: PA.10 _________________________ | ______________| _______________ | |USART | | HyperTerminal | | | | | | | | TX |______________________|RX | | | | | | | | | RS232 Cable | | | | | | | | | RX |______________________|TX | | | | | | | |______________| |_______________| | | | | | | | | |_STM32_Board_____________| @par Keywords Connectivity, UART, Printf, Baud rate, RS-232, HyperTerminal, full-duplex @Note<74>If the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors, <20><><A0><A0><A0>then it is highly recommended to enable the CPU cache and maintain its coherence at application level. <0A><><A0><A0><A0><A0>The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes). @Note It is recommended to enable the cache and maintain its coherence, but depending on the use case <0A><><A0><A0><A0> It is also possible to configure the MPU as "Write through", to guarantee the write access coherence. <0A><><A0><A0><A0><A0>In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable. <0A><><A0><A0><A0><A0>Even though the user must manage the cache coherence for read accesses. <0A><><A0><A0><A0><A0>Please refer to the AN4838 <20>Managing memory protection unit (MPU) in STM32 MCUs<55> <0A><><A0><A0><A0><A0>Please refer to the AN4839 <20>Level 1 cache on STM32F7 Series<65> @par Directory contents - UART/UART_Printf/Inc/stm32f7xx_hal_conf.h HAL configuration file - UART/UART_Printf/Inc/stm32f7xx_it.h Interrupt handlers header file - UART/UART_Printf/Inc/main.h Header for main.c module - UART/UART_Printf/Src/stm32f7xx_it.c Interrupt handlers - UART/UART_Printf/Src/main.c Main program - UART/UART_Printf/Src/stm32f7xx_hal_msp.c HAL MSP module - UART/UART_Printf/Src/system_stm32f7xx.c STM32F7xx system source file @par Hardware and Software environment - This example runs on STM32F756xx/STM32F746xx devices. - This example has been tested with STM327x6G-EVAL board revB and can be easily tailored to any other supported device and development board. - STM32756G_EVAL Set-up - Connect a null-modem female/female RS232 cable between the DB9 connector CN7 (USART1) and PC serial port if you want to display data on the HyperTerminal. @note Make sure that jumper JP7 is on RS232_RX position. - Hyperterminal configuration: - Word Length = 7 Bits - One Stop Bit - Odd parity - BaudRate = 9600 baud - flow control: None @par How to use it ? In order to make the program work, you must do the following : - Open your preferred toolchain - Rebuild all files and load your image into target memory - Run the example */