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126 lines
5.7 KiB
Plaintext
126 lines
5.7 KiB
Plaintext
/**
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@page IWDG_Example Independent Watchdog example
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@verbatim
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******************************************************************************
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* @file IWDG/IWDG_Example/readme.txt
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* @author MCD Application Team
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* @brief Description of the Independent Watchdog example.
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******************************************************************************
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*
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* Copyright (c) 2016 STMicroelectronics. All rights reserved.
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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@endverbatim
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@par Example Description
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This example describes how to reload the IWDG counter and to simulate a software
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fault by generating an MCU IWDG reset when a programmed time period has elapsed.
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At the beginning of the main program the HAL_Init() function is called to reset
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all the peripherals, initialize the Flash interface and the systick.
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Then the SystemClock_Config() function is used to configure the system
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clock (SYSCLK) to run at 216 MHz.
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The IWDG timeout is set to 250 ms (the timeout may vary due to LSI frequency
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dispersion).
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First, the TIM5 timer is configured to measure the LSI frequency as the
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LSI is internally connected to TIM5 CH4, in order to adjust the IWDG clock.
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The LSI measurement using the TIM5 is described below:
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- Configure the TIM5 to remap internally the TIM5 CH4 Input Capture to the LSI
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clock output.
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- Enable the TIM5 Input Capture interrupt: after one cycle of LSI clock, the
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period value is stored in a variable and compared to the HCLK clock to get
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its real value.
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Then, the IWDG reload counter is configured as below to obtain 250 ms according
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to the measured LSI frequency after setting the prescaler value:
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IWDG counter clock Frequency = LSI Frequency / Prescaler value
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The IWDG reload counter is refreshed each 240 ms in the main program infinite
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loop to prevent a IWDG reset.
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LED2 is also toggled each 240 ms indicating that the program is running.
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An EXTI Line is connected to a GPIO pin, and configured to generate an interrupt
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on the rising edge of the signal.
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The EXTI Line is used to simulate a software failure: once the EXTI Line event
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occurs, by pressing the User push-button (PC.13), the corresponding interrupt
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is served.
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In the ISR, a write to invalid address generates a Hardfault exception
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containing an infinite loop and preventing to return to main program (the IWDG
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reload counter is not refreshed).
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As a result, when the IWDG counter reaches 00h, the IWDG reset occurs.
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If the IWDG reset is generated, after the system resumes from reset, LED1 is turned ON.
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If the EXTI Line event does not occur, the IWDG counter is indefinitely refreshed in the main
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program infinite loop, and there is no IWDG reset.
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LED3 is turned ON and remains ON if any error occurs.
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@note Care must be taken when using HAL_Delay(), this function provides accurate
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delay (in milliseconds) based on variable incremented in SysTick ISR. This
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implies that if HAL_Delay() is called from a peripheral ISR process, then
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the SysTick interrupt must have higher priority (numerically lower)
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than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
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To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
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@note The application need to ensure that the SysTick time base is always set to 1 millisecond
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to have correct HAL operation.
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@par Keywords
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System, IWDG, Timeout, Reload Counter, MCU Reset, Downcounter, LSI, Timer, Measure Frequency
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@Note<74>If the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
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<20><><EFBFBD><EFBFBD><EFBFBD>then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
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@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Even though the user must manage the cache coherence for read accesses.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4838 <20>Managing memory protection unit (MPU) in STM32 MCUs<55>
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4839 <20>Level 1 cache on STM32F7 Series<65>
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@par Directory contents
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- IWDG/IWDG_Example/Inc/stm32f7xx_hal_conf.h HAL configuration file
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- IWDG/IWDG_Example/Inc/stm32f7xx_it.h Interrupt handlers header file
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- IWDG/IWDG_Example/Inc/main.h Header for main.c module
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- IWDG/IWDG_Example/Src/stm32f7xx_it.c Interrupt handlers
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- IWDG/IWDG_Example/Src/main.c Main program
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- IWDG/IWDG_Example/Src/stm32f7xx_hal_msp.c HAL MSP file
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- IWDG/IWDG_Example/Src/system_stm32f7xx.c STM32F7xx system source file
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@par Hardware and Software environment
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- This example runs on STM32F767ZI devices.
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- This example has been tested with STM32F767ZI-Nucleo board and can be
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easily tailored to any other supported device and development board.
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@par How to use it ?
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In order to make the program work, you must do the following :
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- Open your preferred toolchain
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- Rebuild all files: Project->Rebuild all
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- Load project image: Project->Download and Debug
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- Run program: Debug->Go(F5)
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* <h3><center>© COPYRIGHT STMicroelectronics</center></h3>
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*/
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