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83 lines
4.0 KiB
Plaintext
83 lines
4.0 KiB
Plaintext
/**
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@page ADC_RegularConversion_Interrupt conversion using interrupt
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@verbatim
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******************************************************************************
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* @file ADC/ADC_RegularConversion_Interrupt/readme.txt
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* @author MCD Application Team
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* @brief Description of the ADC RegularConversion interrupt example.
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******************************************************************************
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*
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* Copyright (c) 2016 STMicroelectronics. All rights reserved.
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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@endverbatim
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@par Example Description
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How to use the ADC in interrupt mode to convert data through the HAL API.
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The ADC1 is configured to convert continuously ADC_CHANNEL_10.
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Each time an end of conversion occurs an interrupt is generated and the converted
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data of ADC1 DR register is affected to the uhADCxConvertedValue variable in the
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ADC conversion complete call back function.
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In this example, the system clock is 216MHz, APB2 = 108MHz and ADC clock = APB2/4.
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Since ADC1 clock is 27 MHz and sampling time is set to 3 cycles, the conversion
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time to 12bit data is 12 cycles so the total conversion time is (12+3)/27= 0.55us(1.8Msps).
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User can vary the ADC_CHANNEL_10 voltage by applying an input voltage on pin PC.00 (pin3 connector 9) (e.g. using function generator).
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The converted value is monitored through debugger using the uhADCxConvertedValue variable
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STM32 Nucleo board's LEDs can be used to monitor the transfer status:
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- LED3 is ON when there is an initialization error.
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@par Keywords
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Analog, ADC, Analog to Digital Converter, Regular Conversion, Interrupt, Continuous Conversion
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@Note If the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
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then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
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The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
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@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
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It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
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In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
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Even though the user must manage the cache coherence for read accesses.
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Please refer to the AN4838 “Managing memory protection unit (MPU) in STM32 MCUs”
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Please refer to the AN4839 “Level 1 cache on STM32F7 Series”
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@par Directory contents
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- ADC/ADC_RegularConversion_Interrupt/Inc/stm32f7xx_hal_conf.h HAL configuration file
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- ADC/ADC_RegularConversion_Interrupt/Inc/stm32f7xx_it.h DMA interrupt handlers header file
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- ADC/ADC_RegularConversion_Interrupt/Inc/main.h Header for main.c module
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- ADC/ADC_RegularConversion_Interrupt/Src/stm32f7xx_it.c DMA interrupt handlers
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- ADC/ADC_RegularConversion_Interrupt/Src/main.c Main program
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- ADC/ADC_RegularConversion_Interrupt/Src/stm32f7xx_hal_msp.c HAL MSP file
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- ADC/ADC_RegularConversion_Interrupt/Src/system_stm32f7xx.c STM32F7xx system source file
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@par Hardware and Software environment
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- This example runs on STM32F767ZI devices.
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- This example has been tested with STM32F767ZI-Nucleo_144 board and can be
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easily tailored to any other supported device and development board.
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@par How to use it ?
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In order to make the program work, you must do the following :
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- Open your preferred toolchain
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- Rebuild all files and load your image into target memory
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- Run the example
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* <h3><center>© COPYRIGHT STMicroelectronics</center></h3>
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*/
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