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121 lines
5.7 KiB
Plaintext
121 lines
5.7 KiB
Plaintext
/**
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@page GPIO_IOToggle GPIO IO Toggle example
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@verbatim
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******************************************************************************
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* @file GPIO/GPIO_IOToggle/readme.txt
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* @author MCD Application Team
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* @brief Description of the GPIO IO Toggle example.
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2018 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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@endverbatim
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@par Example Description
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How to configure and use GPIOs through the HAL API.
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This example provide different configuration with linker files which allows different eXecution schemas
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Supported configuration by STM32F7508-DISCO:
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- XiP From QSPI, Data on Internal SRAM
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- XiP From QSPI, Data on External SDRAM
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- BootROM : Execution From External SDRAM , Data on Internal SRAM
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PI1 IO (configured in output pushpull mode) toggles in a forever loop.
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On STM32F7508-DISCO board this IO is connected to LED1.
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In this example, HCLK is configured at 216 MHz.
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@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
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based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
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a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
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than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
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To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
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@note The application need to ensure that the SysTick time base is always set to 1 millisecond
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to have correct HAL operation.
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@par Keywords
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System, GPIO, Output, Alternate function, Push-pull, Toggle
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@Note<74>If the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
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<20><><EFBFBD><EFBFBD><EFBFBD>then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
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@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Even though the user must manage the cache coherence for read accesses.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4838 <20>Managing memory protection unit (MPU) in STM32 MCUs<55>
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4839 <20>Level 1 cache on STM32F7 Series<65>
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@par Directory contents
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- GPIO/GPIO_IOToggle/Inc/stm32f7xx_hal_conf.h HAL configuration file
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- GPIO/GPIO_IOToggle/Inc/stm32f7xx_it.h Interrupt handlers header file
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- GPIO/GPIO_IOToggle/Inc/main.h Header for main.c module
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- GPIO/GPIO_IOToggle/Src/stm32f7xx_it.c Interrupt handlers
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- GPIO/GPIO_IOToggle/Src/main.c Main program
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- GPIO/GPIO_IOToggle/Src/system_stm32f7xx.c STM32F7xx system source file
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@par Hardware and Software environment
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- This example runs on STM32F7508xx devices.
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- This example has been tested with STM32F7508-DISCO board and can be
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easily tailored to any other supported device and development board.
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@par How to use it ?
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In order to make the program work, you must do the following:
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1. Select required configuration in memory.h in Templates\ExtMem_Boot\Inc.
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The default configuration is:
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- DATA_AREA set to USE_INTERNAL_SRAM
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- CODE_AREA set to USE_QSPI
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2. Program the internal Flash with the ExtMem_Boot (see below).
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3. Program the external memory with your application (see below).
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4. Start debugging user application or reset for free running.
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In order to load the ExtMem_Boot code :
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- Open your preferred toolchain :
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- Open the Project
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- Rebuild all files
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- Load project image
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In order to load the user application to the external memory:
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- Open your preferred toolchain
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- Open the Project
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- Use project matching ExtMem_Boot selected configuration
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- Rebuild all files:
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- Run & debug the program:
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- For an XiP configuration (eXecute in Place from QSPI):
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- Using EWARM or MDK-ARM : Load project image from the IDE: Project->Debug
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- Using SW4STM32 :
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- Open the STM32CubeProgrammer tool
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- Select the QSPI external flash loader "N25Q128A_STM32F7508-DISCO" in case of XiP from QSPI
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- From Erasing & Programming menu, browse and open the output binary file relative to the application
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- Load the file into the external QSPI flash using "Start Programming" at the address APPLICATION_ADDRESS (0x90000000)
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- For a BootROM configuration (BootROM external SDRAM):
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- if BINARY_AREA is USE_SPI_NOR then use the STM32CubeProgarmmer tool, select QSPI external flash loader "N25Q128A_STM32F7508-DISCO"
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and load the Project.bin (application binary output file) to the QSPI memory at the address 0x90000000
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- if BINARY_AREA is USE_SDCARD then copy the project.bin to a micro-SD to be plugged on CN3 and reset the board.
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- In order to debug this example, user shall attach the debugger, and perform a reset
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* <h3><center>© COPYRIGHT STMicroelectronics</center></h3>
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*/
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