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81 lines
3.7 KiB
Plaintext
81 lines
3.7 KiB
Plaintext
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/**
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@page UTILS_ConfigureSystemClock UTILS example
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@verbatim
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******************************************************************************
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* @file Examples_LL/UTILS/UTILS_ConfigureSystemClock/readme.txt
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* @author MCD Application Team
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* @brief Description of the UTILS example.
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******************************************************************************
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*
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* Copyright (c) 2016 STMicroelectronics. All rights reserved.
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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@endverbatim
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@par Example Description
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This example describes how to use UTILS LL API to configure the system clock using PLL with HSI as source
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clock. The user application just needs to calculate PLL parameters using STM32CubeMX and call the UTILS LL
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API.
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System starts with clock used after reset.
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Then, a system clock switch is done to PLL with HSI as PLL clock source. Automatically, FLASH latency
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is tuned according to system constraints described in the reference manual.
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User can easily set its own PLL parameters in changing global variable used to store them.
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A LED1 toggle of 1sec provides this information that system is well configured to requested frequency.
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Anyway, signal on PA.08 can be monitored with an oscilloscope (in connecting PA.08 to pin 8 of PA_PORT)
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to check the requested frequency:
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- SYSCLK frequency with frequency value around @216MHz.
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@par Keywords
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Utils, system, Clock, HSI, PLL, flash latency, SYSCLK, frequencyn Oscilloscope
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@Note<74>If the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
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<20><><EFBFBD><EFBFBD><EFBFBD>then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
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@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Even though the user must manage the cache coherence for read accesses.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4838 <20>Managing memory protection unit (MPU) in STM32 MCUs<55>
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4839 <20>Level 1 cache on STM32F7 Series<65>
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@par Directory contents
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- UTILS/UTILS_ConfigureSystemClock/Inc/stm32f7xx_it.h Interrupt handlers header file
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- UTILS/UTILS_ConfigureSystemClock/Inc/main.h Header for main.c module
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- UTILS/UTILS_ConfigureSystemClock/Inc/stm32_assert.h Template file to include assert_failed function
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- UTILS/UTILS_ConfigureSystemClock/Src/stm32f7xx_it.c Interrupt handlers
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- UTILS/UTILS_ConfigureSystemClock/Src/main.c Main program
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- UTILS/UTILS_ConfigureSystemClock/Src/system_stm32f7xx.c STM32F7xx system source file
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@par Hardware and Software environment
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- This example runs on STM32F767xx devices.
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- This example has been tested with NUCLEO-F767ZI board and can be
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easily tailored to any other supported device and development board.
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@par How to use it ?
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In order to make the program work, you must do the following :
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- Open your preferred toolchain
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- Rebuild all files and load your image into target memory
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- Run the example
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* <h3><center>© COPYRIGHT STMicroelectronics</center></h3>
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*/
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