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119 lines
6.1 KiB
Plaintext
119 lines
6.1 KiB
Plaintext
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/**
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@page FreeRTOS_SemaphoreFromISR FreeRTOS semaphore from ISR application
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@verbatim
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******************** (C) COPYRIGHT 2016 STMicroelectronics *******************
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* @file FreeRTOS/FreeRTOS_SemaphoreFromISR/readme.txt
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* @author MCD Application Team
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* @brief Description of the FreeRTOS semaphore from ISR application.
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******************************************************************************
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*
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* Copyright (c) 2017 STMicroelectronics International N.V. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted, provided that the following conditions are met:
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*
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* 1. Redistribution of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of other
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* contributors to this software may be used to endorse or promote products
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* derived from this software without specific written permission.
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* 4. This software, including modifications and/or derivative works of this
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* software, must execute solely and exclusively on microcontroller or
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* microprocessor devices manufactured by or for STMicroelectronics.
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* 5. Redistribution and use of this software other than as permitted under
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* this license is void and will automatically terminate your rights under
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* this license.
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*
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* THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
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* PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
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* RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
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* SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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@endverbatim
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@par Description
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How to use semaphore from ISR with CMSIS RTOS API.
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This application creates a thread that toggles LED through semaphore given from ISR.
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Each time the user pushes the TAMPER button of the EVAL board the semaphore
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is given to the SemaphoreTest Thread to toggle the LED1
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@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
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based on variable incremented in HAL time base ISR. This implies that if HAL_Delay() is called from
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a peripheral ISR process, then the HAL time base interrupt must have higher priority (numerically lower)
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than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
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To change the HAL time base interrupt priority you have to use HAL_NVIC_SetPriority() function.
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@note The application needs to ensure that the HAL time base is always set to 1 millisecond
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to have correct HAL operation.
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@note The FreeRTOS heap size configTOTAL_HEAP_SIZE defined in FreeRTOSConfig.h is set according to
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the OS resources memory requirements of the application with +10% margin and rounded to the
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upper Kbyte boundary.
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For more details about FreeRTOS implementation on STM32Cube, please refer to UM1722 "Developing Applications
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on STM32Cube with RTOS".
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@par Keywords
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Middleware, RTOS, FreeRTOS, Thread, Semaphore, Priorities, ISR, Interrupt
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@Note<74>If the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
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<20><><EFBFBD><EFBFBD><EFBFBD>then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
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@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Even though the user must manage the cache coherence for read accesses.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4838 <20>Managing memory protection unit (MPU) in STM32 MCUs<55>
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4839 <20>Level 1 cache on STM32F7 Series<65>
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@par Directory contents
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- FreeRTOS/FreeRTOS_SemaphoreFromISR/Inc/main.h Main program header file
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- FreeRTOS/FreeRTOS_SemaphoreFromISR/Inc/stm32f7xx_hal_conf.h HAL Library Configuration file
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- FreeRTOS/FreeRTOS_SemaphoreFromISR/Inc/stm32f7xx_it.h Interrupt handlers header file
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- FreeRTOS/FreeRTOS_SemaphoreFromISR/Inc/FreeRTOSConfig.h FreeRTOS Configuration file
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- FreeRTOS/FreeRTOS_SemaphoreFromISR/Src/main.c Main program
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- FreeRTOS/FreeRTOS_SemaphoreFromISR/Src/stm32f7xx_it.c Interrupt handlers
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@par Hardware and Software environment
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- This application runs on STM32F756xx/STM32F746xx devices.
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- This example has been tested with STM327x6G_EVAL evaluation board and can be
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easily tailored to any other supported device and development board.
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- STM327x6G_EVAL Set-up
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- Ensure that JP24 is in position 2-3 to use LED1.
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@par How to use it ?
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In order to make the program work, you must do the following :
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- Open your preferred toolchain
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- Rebuild all files and load your image into target memory
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- Run the example
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* <h3><center>© COPYRIGHT STMicroelectronics</center></h3>
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*/
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