mirror of
https://github.com/STMicroelectronics/STM32CubeF4.git
synced 2025-05-02 22:17:06 +08:00
167 lines
8.7 KiB
C
167 lines
8.7 KiB
C
/**
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******************************************************************************
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* @file DFSDM/DFSDM_PulseSkipper/Inc/main.h
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* @author MCD Application Team
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* @brief Header for main.c module
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __MAIN_H
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#define __MAIN_H
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx_hal.h"
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#include "stm32f413h_discovery.h"
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#include "audio.h"
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#include "pulse_skipper.h"
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#include "../Components/wm8994/wm8994.h"
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/* Exported types ------------------------------------------------------------*/
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/* Exported constants --------------------------------------------------------*/
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/* Exported macro ------------------------------------------------------------*/
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/* Exported functions ------------------------------------------------------- */
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void Error_Handler(void);
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/* Unselect USE_CHANNEL_DELAY for normal use of the DFSDM */
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#define USE_CHANNEL_DELAY
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/* Select Mics */
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//#define PLAY_DFSDM2_DATIN01 /* Use Mics: U2 and U3 from extention board */
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#define PLAY_DFSDM2_DATIN06 /* Use Mics: U2 and U5 from extention board */
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//#define PLAY_DFSDM2_DATIN07 /* Use Mics: U2 and U4 from extention board */
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//#define PLAY_DFSDM2_DATIN16 /* Use Mics: U3 and U5 from extention board */
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//#define PLAY_DFSDM2_DATIN17 /* Use Mics: U3 and U4 from extention board */
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//#define PLAY_DFSDM2_DATIN67 /* Use Mics: U5 and U4 from extention board */
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//#define PLAY_DFSDM12_DATIN10 /* Use Mics: U1 and U2 from extention board or U16 and U17 from discovery */
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//#define PLAY_DFSDM12_DATIN11 /* Use Mics: U1 and U3 from extention board */
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//#define PLAY_DFSDM12_DATIN16 /* Use Mics: U1 and U5 from extention board */
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//#define PLAY_DFSDM12_DATIN17 /* Use Mics: U1 and U4 from extention board */
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#if defined(USE_CHANNEL_DELAY)
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#if defined(PLAY_DFSDM2_DATIN01)
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/* Select channel to generate delay: either DFSDM2 CH0 or DFSDM2 CH1 */
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//#define GENERATE_DELAY_DFSDM2_CH1
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//#define GENERATE_DELAY_DFSDM2_CH0
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#elif defined(PLAY_DFSDM2_DATIN06)
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/* Select channel to generate delay: either DFSDM2 CH0 or DFSDM2 CH6 */
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//#define GENERATE_DELAY_DFSDM2_CH6
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//#define GENERATE_DELAY_DFSDM2_CH0
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#elif defined(PLAY_DFSDM2_DATIN07)
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/* Select channel to generate delay: either DFSDM2 CH0 or DFSDM2 CH7 */
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//#define GENERATE_DELAY_DFSDM2_CH7
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//#define GENERATE_DELAY_DFSDM2_CH0
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#elif defined(PLAY_DFSDM2_DATIN16)
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/* Select channel to generate delay: either DFSDM2 CH1 or DFSDM2 CH6 */
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//#define GENERATE_DELAY_DFSDM2_CH1
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//#define GENERATE_DELAY_DFSDM2_CH6
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#elif defined(PLAY_DFSDM2_DATIN17)
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/* Select channel to generate delay: either DFSDM2 CH1 or DFSDM2 CH7 */
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//#define GENERATE_DELAY_DFSDM2_CH1
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#define GENERATE_DELAY_DFSDM2_CH7
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#elif defined(PLAY_DFSDM2_DATIN67)
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/* Select channel to generate delay: either DFSDM2 CH6 or DFSDM2 CH7 */
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#define GENERATE_DELAY_DFSDM2_CH6
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//#define GENERATE_DELAY_DFSDM2_CH7
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#elif defined(PLAY_DFSDM12_DATIN10)
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/* Select channel to generate delay: either DFSDM1 CH1 or DFSDM2 CH0 */
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//#define GENERATE_DELAY_DFSDM1_CH1
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#define GENERATE_DELAY_DFSDM2_CH0
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#elif defined(PLAY_DFSDM12_DATIN11)
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/* Select channel to generate delay: either DFSDM1 CH1 or DFSDM2 CH1 */
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//#define GENERATE_DELAY_DFSDM1_CH1
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#define GENERATE_DELAY_DFSDM2_CH1 /* OK */
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#elif defined(PLAY_DFSDM12_DATIN16)
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/* Select channel to generate delay: either DFSDM1 CH1 or DFSDM2 CH6 */
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//#define GENERATE_DELAY_DFSDM1_CH1
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//#define GENERATE_DELAY_DFSDM2_CH6
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#elif defined(PLAY_DFSDM12_DATIN17)
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/* Select channel to generate delay: either DFSDM1 CH1 or DFSDM2 CH7 */
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//#define GENERATE_DELAY_DFSDM1_CH1
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//#define GENERATE_DELAY_DFSDM2_CH7
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#endif
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#endif
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#define DFSDM_DATIN0_CHANNEL DFSDM_CHANNEL_0
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#define DFSDM_DATIN1_CHANNEL DFSDM_CHANNEL_1
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#define DFSDM_DATIN2_CHANNEL DFSDM_CHANNEL_2
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#define DFSDM_DATIN3_CHANNEL DFSDM_CHANNEL_3
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#define DFSDM_DATIN4_CHANNEL DFSDM_CHANNEL_4
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#define DFSDM_DATIN5_CHANNEL DFSDM_CHANNEL_5
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#define DFSDM_DATIN6_CHANNEL DFSDM_CHANNEL_6
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#define DFSDM_DATIN7_CHANNEL DFSDM_CHANNEL_7
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#define DFSDM1_DATIN0_INSTANCE DFSDM1_Channel0
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#define DFSDM1_DATIN1_INSTANCE DFSDM1_Channel1
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#define DFSDM1_DATIN2_INSTANCE DFSDM1_Channel2
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#define DFSDM1_DATIN3_INSTANCE DFSDM1_Channel3
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#define DFSDM1_FILTER0 DFSDM1_Filter0
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#define DFSDM1_FILTER1 DFSDM1_Filter1
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#define DFSDM2_DATIN0_INSTANCE DFSDM2_Channel0
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#define DFSDM2_DATIN1_INSTANCE DFSDM2_Channel1
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#define DFSDM2_DATIN2_INSTANCE DFSDM2_Channel2
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#define DFSDM2_DATIN3_INSTANCE DFSDM2_Channel3
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#define DFSDM2_DATIN4_INSTANCE DFSDM2_Channel4
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#define DFSDM2_DATIN5_INSTANCE DFSDM2_Channel5
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#define DFSDM2_DATIN6_INSTANCE DFSDM2_Channel6
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#define DFSDM2_DATIN7_INSTANCE DFSDM2_Channel7
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#define DFSDM2_FILTER0 DFSDM2_Filter0
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#define DFSDM2_FILTER1 DFSDM2_Filter1
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#define DFSDM2_FILTER2 DFSDM2_Filter2
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#define DFSDM2_FILTER3 DFSDM2_Filter3
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#define DFSDM1_CKOUT_PIN GPIO_PIN_8
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#define DFSDM1_CKOUT_PORT GPIOA
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#define DFSDM1_CKOUT_ALTERNATE GPIO_AF6_DFSDM1
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#define __DFSDM1_CKOUT_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
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#define __DFSDM1_CKOUT_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE()
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#define DFSDM2_CKOUT_PIN GPIO_PIN_2
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#define DFSDM2_CKOUT_PORT GPIOD
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#define DFSDM2_CKOUT_ALTERNATE GPIO_AF3_DFSDM2
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#define __DFSDM2_CKOUT_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
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#define __DFSDM2_CKOUT_DISABLE() __HAL_RCC_GPIOD_CLK_DISABLE()
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#define DFSDM1_DATIN1_PIN GPIO_PIN_6
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#define DFSDM1_DATIN1_PORT GPIOD
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#define DFSDM1_DATIN1_ALTERNATE GPIO_AF6_DFSDM1
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#define __DFSDM1_DATIN1_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
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#define __DFSDM1_DATIN1_DISABLE() __HAL_RCC_GPIOD_CLK_DISABLE()
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#define DFSDM2_DATIN1_PIN GPIO_PIN_7
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#define DFSDM2_DATIN1_PORT GPIOA
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#define DFSDM2_DATIN1_ALTERNATE GPIO_AF7_DFSDM2
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#define __DFSDM2_DATIN1_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
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#define __DFSDM2_DATIN1_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE()
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#define DFSDM2_DATIN7_PIN GPIO_PIN_7
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#define DFSDM2_DATIN7_PORT GPIOB
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#define DFSDM2_DATIN7_ALTERNATE GPIO_AF6_DFSDM2
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#define __DFSDM2_DATIN7_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
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#define __DFSDM2_DATIN7_DISABLE() __HAL_RCC_GPIOB_CLK_DISABLE()
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#define __HAL_RCC_DFSDMx_CLK_ENABLE() do {__HAL_RCC_DFSDM1_CLK_ENABLE(); \
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__HAL_RCC_DFSDM2_CLK_ENABLE(); \
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}while(0)
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#define __HAL_RCC_DFSDMxAUDIO_CONFIG() do {__HAL_RCC_DFSDM1AUDIO_CONFIG(RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1); \
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__HAL_RCC_DFSDM2AUDIO_CONFIG(RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1); \
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}while(0)
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#endif /* __MAIN_H */
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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