mirror of
https://github.com/STMicroelectronics/STM32CubeF4.git
synced 2025-05-03 22:17:07 +08:00
144 lines
5.4 KiB
C
144 lines
5.4 KiB
C
/**
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******************************************************************************
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* @file QSPI/QSPI_PreInitConfig/Inc/main.h
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* @author MCD Application Team
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* @brief Header for main.c module
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __MAIN_H
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#define __MAIN_H
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx_hal.h"
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#include "stm32412g_discovery.h"
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/* Exported types ------------------------------------------------------------*/
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/* Exported constants --------------------------------------------------------*/
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/* Definition for QSPI clock resources */
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#define QSPI_CLK_ENABLE() __HAL_RCC_QSPI_CLK_ENABLE()
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#define QSPI_CLK_DISABLE() __HAL_RCC_QSPI_CLK_DISABLE()
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#define QSPI_CS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE()
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#define QSPI_CLK_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
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#define QSPI_D0_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE()
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#define QSPI_D1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE()
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#define QSPI_D2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE()
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#define QSPI_D3_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE()
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#define QSPI_DMA_CLK_ENABLE() __HAL_RCC_DMA2_CLK_ENABLE()
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#define QSPI_FORCE_RESET() __HAL_RCC_QSPI_FORCE_RESET()
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#define QSPI_RELEASE_RESET() __HAL_RCC_QSPI_RELEASE_RESET()
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/* Definition for QSPI Pins */
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#define QSPI_CS_PIN GPIO_PIN_6
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#define QSPI_CS_GPIO_PORT GPIOG
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#define QSPI_CLK_PIN GPIO_PIN_2
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#define QSPI_CLK_GPIO_PORT GPIOB
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#define QSPI_D0_PIN GPIO_PIN_8
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#define QSPI_D0_GPIO_PORT GPIOF
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#define QSPI_D1_PIN GPIO_PIN_9
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#define QSPI_D1_GPIO_PORT GPIOF
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#define QSPI_D2_PIN GPIO_PIN_7
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#define QSPI_D2_GPIO_PORT GPIOF
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#define QSPI_D3_PIN GPIO_PIN_6
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#define QSPI_D3_GPIO_PORT GPIOF
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/* Definition for QSPI DMA */
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#define QSPI_DMA_INSTANCE DMA2_Stream7
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#define QSPI_DMA_CHANNEL DMA_CHANNEL_3
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#define QSPI_DMA_IRQ DMA2_Stream7_IRQn
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#define QSPI_DMA_IRQ_HANDLER DMA2_Stream7_IRQHandler
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/* N25Q128A13EF840E Micron memory */
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/* Size of the flash */
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#define QSPI_FLASH_SIZE 23
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#define QSPI_PAGE_SIZE 256
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#define QSPI_SECTOR_SIZE 4096
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/* Reset Operations */
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#define RESET_ENABLE_CMD 0x66
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#define RESET_MEMORY_CMD 0x99
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/* Identification Operations */
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#define READ_ID_CMD 0x9E
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#define READ_ID_CMD2 0x9F
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#define MULTIPLE_IO_READ_ID_CMD 0xAF
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#define READ_SERIAL_FLASH_DISCO_PARAM_CMD 0x5A
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/* Read Operations */
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#define READ_CMD 0x03
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#define FAST_READ_CMD 0x0B
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#define DUAL_OUT_FAST_READ_CMD 0x3B
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#define DUAL_INOUT_FAST_READ_CMD 0xBB
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#define QUAD_OUT_FAST_READ_CMD 0x6B
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#define QUAD_INOUT_FAST_READ_CMD 0xEB
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/* Write Operations */
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#define WRITE_ENABLE_CMD 0x06
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#define WRITE_DISABLE_CMD 0x04
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/* Register Operations */
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#define READ_STATUS_REG_CMD 0x05
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#define WRITE_STATUS_REG_CMD 0x01
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#define READ_LOCK_REG_CMD 0xE8
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#define WRITE_LOCK_REG_CMD 0xE5
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#define READ_FLAG_STATUS_REG_CMD 0x70
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#define CLEAR_FLAG_STATUS_REG_CMD 0x50
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#define READ_NONVOL_CFG_REG_CMD 0xB5
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#define WRITE_NONVOL_CFG_REG_CMD 0xB1
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#define READ_VOL_CFG_REG_CMD 0x85
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#define WRITE_VOL_CFG_REG_CMD 0x81
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#define READ_ENHANCED_VOL_CFG_REG_CMD 0x65
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#define WRITE_ENHANCED_VOL_CFG_REG_CMD 0x61
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/* Program Operations */
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#define PAGE_PROG_CMD 0x02
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#define DUAL_IN_FAST_PROG_CMD 0xA2
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#define EXT_DUAL_IN_FAST_PROG_CMD 0xD2
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#define QUAD_IN_FAST_PROG_CMD 0x32
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#define EXT_QUAD_IN_FAST_PROG_CMD 0x12
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/* Erase Operations */
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#define SUBSECTOR_ERASE_CMD 0x20
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#define SECTOR_ERASE_CMD 0xD8
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#define BULK_ERASE_CMD 0xC7
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#define PROG_ERASE_RESUME_CMD 0x7A
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#define PROG_ERASE_SUSPEND_CMD 0x75
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/* One-Time Programmable Operations */
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#define READ_OTP_ARRAY_CMD 0x4B
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#define PROG_OTP_ARRAY_CMD 0x42
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/* Default dummy clocks cycles */
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#define DUMMY_CLOCK_CYCLES_READ 8
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#define DUMMY_CLOCK_CYCLES_READ_QUAD 10
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/* End address of the QSPI memory */
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#define QSPI_END_ADDR (1 << QSPI_FLASH_SIZE)
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/* Size of buffers */
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#define BUFFERSIZE (COUNTOF(aTxBuffer) - 1)
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/* Exported macro ------------------------------------------------------------*/
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#define COUNTOF(__BUFFER__) (sizeof(__BUFFER__) / sizeof(*(__BUFFER__)))
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/* Exported functions ------------------------------------------------------- */
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#endif /* __MAIN_H */
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