mirror of
https://github.com/STMicroelectronics/STM32CubeF4.git
synced 2025-05-05 19:29:25 +08:00
528 lines
16 KiB
C
528 lines
16 KiB
C
/**
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******************************************************************************
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* @file QSPI/QSPI_ReadWrite_IT/Src/main.c
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* @author MCD Application Team
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* @brief This example describes how to configure and use QuadSPI through
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* the STM32F4xx HAL API.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "main.h"
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/** @addtogroup STM32F4xx_HAL_Examples
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* @{
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*/
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/** @addtogroup QSPI_ReadWrite_IT
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* @{
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*/
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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QSPI_HandleTypeDef QSPIHandle;
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__IO uint8_t CmdCplt, RxCplt, TxCplt, StatusMatch, TimeOut;
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/* Buffer used for transmission */
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uint8_t aTxBuffer[] = " ****QSPI communication based on IT**** ****QSPI communication based on IT**** ****QSPI communication based on IT**** ****QSPI communication based on IT**** ****QSPI communication based on IT**** ****QSPI communication based on IT**** ";
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/* Buffer used for reception */
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uint8_t aRxBuffer[BUFFERSIZE];
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/* Private function prototypes -----------------------------------------------*/
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static void SystemClock_Config(void);
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static void Error_Handler(void);
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static void QSPI_WriteEnable(QSPI_HandleTypeDef *hqspi);
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static void QSPI_AutoPollingMemReady(QSPI_HandleTypeDef *hqspi);
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static void QSPI_DummyCyclesCfg(QSPI_HandleTypeDef *hqspi);
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/* Private functions ---------------------------------------------------------*/
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/**
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* @brief Main program
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* @param None
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* @retval None
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*/
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int main(void)
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{
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QSPI_CommandTypeDef sCommand;
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uint32_t address = 0;
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uint16_t index;
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__IO uint8_t step = 0;
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/* STM32F4xx HAL library initialization:
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- Configure the Flash prefetch
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- Systick timer is configured by default as source of time base, but user
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can eventually implement his proper time base source (a general purpose
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timer for example or other time source), keeping in mind that Time base
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duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
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handled in milliseconds basis.
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- Set NVIC Group Priority to 4
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- Low Level Initialization
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*/
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HAL_Init();
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/* Configure the system clock to 100 MHz */
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SystemClock_Config();
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BSP_LED_Init(LED3);
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BSP_LED_Init(LED4);
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/* Initialize QuadSPI ------------------------------------------------------ */
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QSPIHandle.Instance = QUADSPI;
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HAL_QSPI_DeInit(&QSPIHandle);
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QSPIHandle.Init.ClockPrescaler = 0;
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QSPIHandle.Init.FifoThreshold = 4;
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QSPIHandle.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE;
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QSPIHandle.Init.FlashSize = QSPI_FLASH_SIZE;
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QSPIHandle.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_2_CYCLE;
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QSPIHandle.Init.ClockMode = QSPI_CLOCK_MODE_0;
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QSPIHandle.Init.FlashID = QSPI_FLASH_ID_1;
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QSPIHandle.Init.DualFlash = QSPI_DUALFLASH_DISABLE;
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if (HAL_QSPI_Init(&QSPIHandle) != HAL_OK)
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{
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Error_Handler();
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}
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sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE;
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sCommand.AddressSize = QSPI_ADDRESS_24_BITS;
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sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
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sCommand.DdrMode = QSPI_DDR_MODE_DISABLE;
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sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
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sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
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while(1)
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{
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switch(step)
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{
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case 0:
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CmdCplt = 0;
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/* Initialize Reception buffer --------------------------------------- */
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for (index = 0; index < BUFFERSIZE; index++)
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{
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aRxBuffer[index] = 0;
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}
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/* Enable write operations ------------------------------------------- */
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QSPI_WriteEnable(&QSPIHandle);
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/* Erasing Sequence -------------------------------------------------- */
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sCommand.Instruction = SECTOR_ERASE_CMD;
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sCommand.AddressMode = QSPI_ADDRESS_1_LINE;
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sCommand.Address = address;
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sCommand.DataMode = QSPI_DATA_NONE;
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sCommand.DummyCycles = 0;
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if (HAL_QSPI_Command_IT(&QSPIHandle, &sCommand) != HAL_OK)
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{
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Error_Handler();
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}
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step++;
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break;
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case 1:
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if(CmdCplt != 0)
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{
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CmdCplt = 0;
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StatusMatch = 0;
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/* Configure automatic polling mode to wait for end of erase ------- */
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QSPI_AutoPollingMemReady(&QSPIHandle);
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step++;
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}
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break;
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case 2:
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if(StatusMatch != 0)
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{
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StatusMatch = 0;
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TxCplt = 0;
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/* Enable write operations ----------------------------------------- */
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QSPI_WriteEnable(&QSPIHandle);
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/* Writing Sequence ------------------------------------------------ */
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sCommand.Instruction = EXT_QUAD_IN_FAST_PROG_CMD;
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sCommand.AddressMode = QSPI_ADDRESS_4_LINES;
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sCommand.DataMode = QSPI_DATA_4_LINES;
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sCommand.NbData = BUFFERSIZE;
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if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
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{
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Error_Handler();
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}
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if (HAL_QSPI_Transmit_IT(&QSPIHandle, aTxBuffer) != HAL_OK)
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{
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Error_Handler();
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}
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step++;
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}
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break;
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case 3:
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if(TxCplt != 0)
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{
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TxCplt = 0;
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StatusMatch = 0;
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/* Configure automatic polling mode to wait for end of program ----- */
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QSPI_AutoPollingMemReady(&QSPIHandle);
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step++;
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}
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break;
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case 4:
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if(StatusMatch != 0)
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{
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StatusMatch = 0;
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RxCplt = 0;
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/* Configure Volatile Configuration register (with new dummy cycles) */
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QSPI_DummyCyclesCfg(&QSPIHandle);
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/* Reading Sequence ------------------------------------------------ */
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sCommand.Instruction = QUAD_INOUT_FAST_READ_CMD;
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sCommand.DummyCycles = DUMMY_CLOCK_CYCLES_READ_QUAD;
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if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
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{
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Error_Handler();
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}
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if (HAL_QSPI_Receive_IT(&QSPIHandle, aRxBuffer) != HAL_OK)
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{
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Error_Handler();
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}
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step++;
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}
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break;
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case 5:
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if (RxCplt != 0)
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{
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RxCplt = 0;
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/* Result comparison ----------------------------------------------- */
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for (index = 0; index < BUFFERSIZE; index++)
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{
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if (aRxBuffer[index] != aTxBuffer[index])
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{
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BSP_LED_On(LED4);
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}
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}
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BSP_LED_Toggle(LED3);
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address += QSPI_PAGE_SIZE;
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if(address >= QSPI_END_ADDR)
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{
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address = 0;
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}
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step = 0;
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}
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break;
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default :
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Error_Handler();
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}
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}
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}
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/**
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* @brief Command completed callbacks.
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* @param hqspi: QSPI handle
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* @retval None
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*/
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void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
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{
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CmdCplt++;
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}
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/**
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* @brief Rx Transfer completed callbacks.
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* @param hqspi: QSPI handle
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* @retval None
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*/
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void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
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{
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RxCplt++;
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}
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/**
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* @brief Tx Transfer completed callbacks.
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* @param hqspi: QSPI handle
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* @retval None
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*/
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void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
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{
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TxCplt++;
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}
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/**
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* @brief Status Match callbacks
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* @param hqspi: QSPI handle
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* @retval None
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*/
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void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
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{
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StatusMatch++;
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}
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/**
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* @brief System Clock Configuration
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* The system Clock is configured as follow :
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* System Clock source = PLL (HSE)
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* SYSCLK(Hz) = 100000000
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* HCLK(Hz) = 100000000
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* AHB Prescaler = 1
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* APB1 Prescaler = 2
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* APB2 Prescaler = 1
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* HSE Frequency(Hz) = 8000000
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* PLL_M = 8
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* PLL_N = 200
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* PLL_P = 2
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* PLL_Q = 7
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* PLL_R = 2
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* VDD(V) = 3.3
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* Main regulator output voltage = Scale1 mode
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* Flash Latency(WS) = 3
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* @param None
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* @retval None
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*/
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static void SystemClock_Config(void)
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{
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RCC_ClkInitTypeDef RCC_ClkInitStruct;
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RCC_OscInitTypeDef RCC_OscInitStruct;
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HAL_StatusTypeDef ret = HAL_OK;
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/* Enable Power Control clock */
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__HAL_RCC_PWR_CLK_ENABLE();
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/* The voltage scaling allows optimizing the power consumption when the device is
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clocked below the maximum system frequency, to update the voltage scaling value
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regarding system frequency refer to product datasheet. */
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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/* Enable HSE Oscillator and activate PLL with HSE as source */
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = 8;
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RCC_OscInitStruct.PLL.PLLN = 200;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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RCC_OscInitStruct.PLL.PLLQ = 7;
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RCC_OscInitStruct.PLL.PLLR = 2;
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ret = HAL_RCC_OscConfig(&RCC_OscInitStruct);
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if(ret != HAL_OK)
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{
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while(1) { ; }
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}
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/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
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clocks dividers */
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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ret = HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3);
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if(ret != HAL_OK)
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{
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while(1) { ; }
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}
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}
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/**
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* @brief This function send a Write Enable and wait it is effective.
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* @param hqspi: QSPI handle
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* @retval None
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*/
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static void QSPI_WriteEnable(QSPI_HandleTypeDef *hqspi)
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{
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QSPI_CommandTypeDef sCommand;
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QSPI_AutoPollingTypeDef sConfig;
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/* Enable write operations ------------------------------------------ */
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sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE;
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sCommand.Instruction = WRITE_ENABLE_CMD;
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sCommand.AddressMode = QSPI_ADDRESS_NONE;
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sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
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sCommand.DataMode = QSPI_DATA_NONE;
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sCommand.DummyCycles = 0;
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sCommand.DdrMode = QSPI_DDR_MODE_DISABLE;
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sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
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sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
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if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
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{
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Error_Handler();
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}
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/* Configure automatic polling mode to wait for write enabling ---- */
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sConfig.Match = 0x02;
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sConfig.Mask = 0x02;
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sConfig.MatchMode = QSPI_MATCH_MODE_AND;
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sConfig.StatusBytesSize = 1;
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sConfig.Interval = 0x10;
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sConfig.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE;
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sCommand.Instruction = READ_STATUS_REG_CMD;
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sCommand.DataMode = QSPI_DATA_1_LINE;
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if (HAL_QSPI_AutoPolling(&QSPIHandle, &sCommand, &sConfig, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
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{
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Error_Handler();
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}
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}
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/**
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* @brief This function read the SR of the memory and wait the EOP.
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* @param hqspi: QSPI handle
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* @retval None
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*/
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static void QSPI_AutoPollingMemReady(QSPI_HandleTypeDef *hqspi)
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{
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QSPI_CommandTypeDef sCommand;
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QSPI_AutoPollingTypeDef sConfig;
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/* Configure automatic polling mode to wait for memory ready ------ */
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sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE;
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sCommand.Instruction = READ_STATUS_REG_CMD;
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sCommand.AddressMode = QSPI_ADDRESS_NONE;
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sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
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sCommand.DataMode = QSPI_DATA_1_LINE;
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sCommand.DummyCycles = 0;
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sCommand.DdrMode = QSPI_DDR_MODE_DISABLE;
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sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
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sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
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sConfig.Match = 0x00;
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sConfig.Mask = 0x01;
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sConfig.MatchMode = QSPI_MATCH_MODE_AND;
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sConfig.StatusBytesSize = 1;
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sConfig.Interval = 0x10;
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sConfig.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE;
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if (HAL_QSPI_AutoPolling_IT(&QSPIHandle, &sCommand, &sConfig) != HAL_OK)
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{
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Error_Handler();
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}
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}
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/**
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* @brief This function configure the dummy cycles on memory side.
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* @param hqspi: QSPI handle
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* @retval None
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*/
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static void QSPI_DummyCyclesCfg(QSPI_HandleTypeDef *hqspi)
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{
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QSPI_CommandTypeDef sCommand;
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uint8_t reg;
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/* Read Volatile Configuration register --------------------------- */
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sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE;
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sCommand.Instruction = READ_VOL_CFG_REG_CMD;
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sCommand.AddressMode = QSPI_ADDRESS_NONE;
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sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
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sCommand.DataMode = QSPI_DATA_1_LINE;
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sCommand.DummyCycles = 0;
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sCommand.DdrMode = QSPI_DDR_MODE_DISABLE;
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sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
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sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
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sCommand.NbData = 1;
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if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
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{
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Error_Handler();
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}
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if (HAL_QSPI_Receive(&QSPIHandle, ®, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
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{
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Error_Handler();
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}
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/* Enable write operations ---------------------------------------- */
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QSPI_WriteEnable(&QSPIHandle);
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/* Write Volatile Configuration register (with new dummy cycles) -- */
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sCommand.Instruction = WRITE_VOL_CFG_REG_CMD;
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MODIFY_REG(reg, 0xF0, (DUMMY_CLOCK_CYCLES_READ_QUAD << POSITION_VAL(0xF0)));
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if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
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{
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Error_Handler();
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}
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if (HAL_QSPI_Transmit(&QSPIHandle, ®, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
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{
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Error_Handler();
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}
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}
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/**
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* @brief This function is executed in case of error occurrence.
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* @param None
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* @retval None
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*/
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static void Error_Handler(void)
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{
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BSP_LED_On(LED4);
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/* User may add here some code to deal with this error */
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while(1)
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{
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HAL_Delay(100);
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BSP_LED_Toggle(LED4);
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}
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}
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#ifdef USE_FULL_ASSERT
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/**
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* @brief Reports the name of the source file and the source line number
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* where the assert_param error has occurred.
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* @param file: pointer to the source file name
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* @param line: assert_param error line source number
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* @retval None
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*/
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void assert_failed(uint8_t *file, uint32_t line)
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{
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/* User can add his own implementation to report the file name and line number,
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ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
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/* Infinite loop */
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while (1)
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{
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}
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}
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#endif
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/**
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* @}
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*/
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/**
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* @}
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*/
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