Attie Grande 216af990d4 Add support for running SYSCLK from PLL1, via PLL2. ...

For parts like the STM32F1 Connectivity Line (STM32F105xx, STM32F107xx),
it is occasionally necessary to source SYSCLK via PLL2. This patch will
add this support.

- Add: `UTILS_GetPLL2OutputFrequency()` to calculate the output frequency of PLL2
- Add: `LL_PLL_ConfigSystemClock_PLL2()` to configure the system clock as sourced from HSE, via PLL2 and PLL1.
- Add: Miscellaneous support definitions.

Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>

2020-12-23 13:47:34 +00:00

..

BSP

Release v1.8.0

2019-07-19 14:54:54 +01:00

CMSIS

Release v1.8.2

2020-10-05 08:36:58 +01:00

STM32F1xx_HAL_Driver

Add support for running SYSCLK from PLL1, via PLL2.

2020-12-23 13:47:34 +00:00