houssine BOUGUERBA a58188598c Release v1.11.4
2023-03-15 11:49:59 +01:00

101 lines
4.0 KiB
C

/**
******************************************************************************
* @file ADC/ADC_Sequencer/Inc/main.h
* @author MCD Application Team
* @brief Header for main.c module
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MAIN_H
#define __MAIN_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
#include "stm32f0xx_nucleo.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Waveform voltage generation for test: */
/* - If this literal is defined: For this example purpose, generates a */
/* waveform voltage on a spare DAC channel, so user has just to connect */
/* a wire between DAC channel output and ADC input to run this example. */
/* (this avoid to user the need of an external signal generator). */
/* - If this literal is not defined: User has to connect an external signal */
/* generator on the selected ADC input to run this example. */
#define WAVEFORM_VOLTAGE_GENERATION_FOR_TEST
/* User can use this section to tailor ADCx instance under use and associated
resources */
/* ## Definition of ADC related resources ################################### */
/* Definition of ADCx clock resources */
#define ADCx ADC1
#define ADCx_CLK_ENABLE() __HAL_RCC_ADC1_CLK_ENABLE()
#define ADCx_FORCE_RESET() __HAL_RCC_ADC1_FORCE_RESET()
#define ADCx_RELEASE_RESET() __HAL_RCC_ADC1_RELEASE_RESET()
/* Definition of ADCx channels */
#define ADCx_CHANNELa ADC_CHANNEL_4
/* Definition of ADCx channels pins */
#define ADCx_CHANNELa_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define ADCx_CHANNELa_GPIO_PORT GPIOA
#define ADCx_CHANNELa_PIN GPIO_PIN_4
/* Definition of ADCx DMA resources */
#define ADCx_DMA_CLK_ENABLE() __HAL_RCC_DMA1_CLK_ENABLE()
#define ADCx_DMA DMA1_Channel1
#define ADCx_DMA_IRQn DMA1_Channel1_IRQn
#define ADCx_DMA_IRQHandler DMA1_Channel1_IRQHandler
/* Definition of ADCx NVIC resources */
#define ADCx_IRQn ADC1_COMP_IRQn
#define ADCx_IRQHandler ADC1_COMP_IRQHandler
#if defined(WAVEFORM_VOLTAGE_GENERATION_FOR_TEST)
/* ## Definition of DAC related resources ################################### */
/* Definition of DACx clock resources */
#define DACx DAC
#define DACx_CLK_ENABLE() __HAL_RCC_DAC1_CLK_ENABLE()
#define DACx_CHANNEL_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define DACx_FORCE_RESET() __HAL_RCC_DAC1_FORCE_RESET()
#define DACx_RELEASE_RESET() __HAL_RCC_DAC1_RELEASE_RESET()
/* Definition of DACx channels */
#define DACx_CHANNEL_TO_ADCx_CHANNELa DAC_CHANNEL_1
/* Definition of DACx channels pins */
#define DACx_CHANNEL_TO_ADCx_CHANNELa_PIN GPIO_PIN_4
#define DACx_CHANNEL_TO_ADCx_CHANNELa_GPIO_PORT GPIOA
/* Definition of DACx NVIC resources */
#define DACx_IRQn TIM6_DAC_IRQn
#define DACx_IRQHandler TIM6_DAC_IRQHandler
#endif /* WAVEFORM_VOLTAGE_GENERATION_FOR_TEST */
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
#endif /* __MAIN_H */