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423 lines
23 KiB
Go
423 lines
23 KiB
Go
package mfrc522
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// Page 0: Command and status
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const (
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// 0x00 // reserved for future use
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regCommand = 0x01 // starts and stops command execution
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// ------------ values --------------------
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// commands, see chapter 10.3, table 149 of the datasheet (only 4 lower bits are used for writing)
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commandRegIdle = 0x00 // no action, cancels current command execution
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commandRegMem = 0x01 // stores 25 bytes into the internal buffer
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commandRegGenerateRandomID = 0x02 // generates a 10-byte random ID number
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commandRegCalcCRC = 0x03 // activates the CRC coprocessor or performs a self-test
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commandRegTransmit = 0x04 // transmits data from the FIFO buffer
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// 0x05, 0x06 not used
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commandRegNoCmdChange = 0x07 // no command change, can be used to modify the Command register bits without
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commandRegReceive = 0x08 // activates the receiver circuits
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// 0x09..0x0B not used
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commandRegTransceive = 0x0C // transmits data from FIFO buffer to antenna and automatically activates the receiver after transmission
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// 0x0D reserved
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commandRegMFAuthent = 0x0E // performs the MIFARE standard authentication as a reader
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commandRegSoftReset = 0x0F // resets the MFRC522
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// starts the wake up procedure during which this bit is read as a logic 1; it is read as a logic 0 when the
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// is ready; Remark: The PowerDown bit cannot be set when the SoftReset command is activated
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commandRegPowerDownBit = 0x10 // Soft power-down mode entered, if 1
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commandRegRcvOffBit = 0x20 // analog part of the receiver is switched off, if 1
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// commandRegReserved67 = 0xC0
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)
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const (
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regComIEn = 0x02 // enable and disable the passing of interrupt requests to IRQ pin
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// ------------ values --------------------
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comIEnRegReset = 0x80 // see table 25 of data sheet
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comIEnRegTimerIEnBit = 0x01 // bit 0: allows the timer interrupt request (TimerIRq bit) to be propagated
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comIEnRegErrIEnBit = 0x02 // bit 1: allows the error interrupt request (ErrIRq bit) to be propagated
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comIEnRegLoAlertIEnBit = 0x04 // bit 2: allows the low alert interrupt request (LoAlertIRq bit) to be propagated
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comIEnRegHiAlertIEnBit = 0x08 // bit 3: allows the high alert interrupt request (HiAlertIRq bit) to be propagated
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comIEnRegIdleIEnBit = 0x10 // bit 4: allows the idle interrupt request (IdleIRq bit) to be propagated
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comIEnRegRxIEnBit = 0x20 // bit 5: allows the receiver interrupt request (RxIRq bit) to be propagated
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comIEnRegTxIEnBit = 0x40 // bit 6: allows the transmitter interrupt request (TxIRq bit) to be propagated
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// 1: signal on pin IRQ is inverted with respect to the Status1 register’s IRq bit
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// 0: signal on pin IRQ is equal to the IRq bit; in combination with the DivIEn register’s IRqPushPull bit, the
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// default value of logic 1 ensures that the output level on pin IRQ is 3-state
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comIEnRegIRqInv = 0x80 // bit 7: see above
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)
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const (
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// ------------ unused commands --------------------
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regDivIEn = 0x03 // enable and disable the passing of interrupt requests to IRQ pin
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)
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const (
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regComIrq = 0x04 // interrupt request bits for communication
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// ------------ values --------------------
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comIrqRegReset = 0x14 // see table 29 of data sheet
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comIrqRegClearAll = 0x7F // all bits are set to clear, except the Set1Bit (0 indicates the reset)
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comIrqRegTimerIRqBit = 0x01 // bit 0: the timer decrements the timer value in register TCounterVal to zero, if 1
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comIrqRegErrIRq1anyBit = 0x02 // bit 1: error bit in the Error register is set, if 1
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// Status1 register’s LoAlert bit is set in opposition to the LoAlert bit, the LoAlertIRq bit stores this event and
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// can only be reset as indicated by the Set1 bit in this register
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comIrqRegLoAlertIRqBit = 0x04 // bit 2: if 1, see above
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// the Status1 register’s HiAlert bit is set in opposition to the HiAlert bit, the HiAlertIRq bit stores this event
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// and can only be reset as indicated by the Set1 bit in this register
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comIrqRegHiAlertIRqBit = 0x08 // bit 3: if 1, see above
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// If a command terminates, for example, when the Command register changes its value from any command to Idle command.
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// If an unknown command is started, the Command register Command[3:0] value changes to the idle state and the
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// IdleIRq bit is set. The microcontroller starting the Idle command does not set the IdleIRq bit.
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comIrqRegIdleIRqBit = 0x10 // bit 4: if 1, see above
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// receiver has detected the end of a valid data stream, if the RxMode register’s RxNoErr bit is set to logic 1,
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// the RxIRq bit is only set to logic 1 when data bytes are available in the FIFO
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comIrqRegRxIRqBit = 0x20 // bit 5: if 1, see above
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comIrqRegTxIRqBit = 0x40 // bit 6: set to 1, immediately after the last bit of the transmitted data was sent out
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// 1: indicates that the marked bits in the register are set
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// 0: indicates that the marked bits in the register are cleared
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comIrqRegSet1Bit = 0x80 // bit 7: see above
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)
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const (
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regDivIrq = 0x05 // diverse interrupt request bits
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// ------------ values --------------------
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divIrqRegReset = 0x00 // see table 31 of data sheet
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//divIrqRegReserved01 = 0x03
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divIrqRegCRCIRqBit = 0x04 // bit 2: the CalcCRC command is active and all data is processed
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//divIrqRegReservedBit3 = 0x08
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// this interrupt is set when either a rising or falling signal edge is detected
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divIrqRegMfinActIRqBit = 0x10 // bit 4: MFIN is active; see above
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//divIrqRegReserved56 = 0x60
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// 1: indicates that the marked bits in the register are set
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// 0: indicates that the marked bits in the register are cleared
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divIrqRegSet2Bit = 0x80 // bit 7: see above
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)
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const (
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regError = 0x06 // error bits showing the error status of the last command executed
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// ------------ values --------------------
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errorRegReset = 0x00 // see table 33 of data sheet
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// set to logic 1 if the SOF is incorrect automatically cleared during receiver start-up phase bit is only valid for
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// 106 kBd; during the MFAuthent command, the ProtocolErr bit is set to logic 1 if the number of bytes received in one
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// data stream is incorrect
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errorRegProtocolErrBit = 0x01 // bit 0: see above
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// automatically cleared during receiver start-up phase; only valid for ISO/IEC 14443 A/MIFARE communication at 106 kBd
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errorRegParityErrBit = 0x02 // bit 1: parity check failed, see above
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// the RxMode register’s RxCRCEn bit is set and the CRC calculation fails automatically; cleared to logic 0 during
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// receiver start-up phase
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errorRegCRCErrBit = 0x04 // bit 2: see above
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// cleared automatically at receiver start-up phase; only valid during the bitwise anticollision at 106 kBd; always
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// set to logic 0 during communication protocols at 212 kBd, 424 kBd and 848 kBd
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errorRegCollErrBit = 0x08 // bit 3: a bit-collision is detected, see above
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//the host or a MFRC522’s internal state machine (e.g. receiver) tries to write data to the FIFO buffer even though
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// it is already full
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errorRegBufferOvflBit = 0x10 // bit 4: FIFO is full, see above
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//errorRegReservedBit5 = 0x20
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// the antenna drivers are automatically switched off
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errorRegTempErrBit = 0x40 // bit 6: internal temperature sensor detects overheating, see above
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// data is written into the FIFO buffer by the host during the MFAuthent command or if data is written into the FIFO
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// buffer by the host during the time between sending the last bit on the RF interface and receiving the last bit on
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// the RF interface
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errorRegWrErrBit = 0x80 // bit 7: see above
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)
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const (
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// ------------ unused commands --------------------
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regStatus1 = 0x07 // communication status bits
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)
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const (
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regStatus2 = 0x08 // receiver and transmitter status bits
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// ------------ values --------------------
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status2RegReset = 0x00 // see table 37 of data sheet
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// bit 0..2 shows the state of the transmitter and receiver state machines
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status2RegModemStateIdle = 0x00 // idle
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status2RegModemStateWait = 0x01 // wait for the BitFraming register’s StartSend bit
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// the minimum time for TxWait is defined by the TxWait register
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status2RegModemStateTxWait = 0x02 // wait until RF field is present if the TMode register’s TxWaitRF bit is set to logic 1
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status2RegModemStateTransmitting = 0x03
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// the minimum time for RxWait is defined by the RxWait register
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status2RegModemStateRxWait = 0x04 // wait until RF field is present if the TMode register’s TxWaitRF bit is set to logic 1
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status2RegModemStateWaitForData = 0x05
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status2RegModemStateReceiving = 0x06
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// all data communication with the card is encrypted; can only be set to logic 1 by a successful execution of the
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// MFAuthent command; only valid in Read/Write mode for MIFARE standard cards; this bit is cleared by software
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status2RegMFCrypto1OnBit = 0x08 // bit 3: indicates that the MIFARE Crypto1 unit is switched on and, see above
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//status2RegReserved45 = 0x30
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// 1: the I2C-bus input filter is set to the High-speed mode independent of the I2C-bus protocol
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// 0: the I2C-bus input filter is set to the I2C-bus protocol used
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status2RegI2cForceHSBit = 0x40 // I2C-bus input filter settings, see above
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status2RegTempSensClear1Bit = 0x80 // clears the temperature error if the temperature is below the alarm limit of 125C
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)
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const (
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regFIFOData = 0x09 // input and output of 64 byte FIFO buffer
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)
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const (
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regFIFOLevel = 0x0A // number of bytes stored in the FIFO buffer
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// ------------ values --------------------
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fifoLevelRegReset = 0x00 // see table 41 of data sheet
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// indicates the number of bytes stored in the FIFO buffer writing to the FIFOData register increments and reading
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// decrements the FIFOLevel value
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fifoLevelRegValue = 0x7F // bit 0..6: see above
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// immediately clears the internal FIFO buffer’s read and write pointer and Error register’s BufferOvfl bit reading
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// this bit always returns 0
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fifoLevelRegFlushBufferBit = 0x80 // bit 7: see above
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)
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const (
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// ------------ unused commands --------------------
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regWaterLevel = 0x0B // level for FIFO underflow and overflow warning
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)
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const (
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regControl = 0x0C // miscellaneous control registers
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// ------------ values --------------------
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controlRegReset = 0x10 // see table 45 of data sheet
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// indicates the number of valid bits in the last received byte
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// if this value is 000b, the whole byte is valid
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controlRegRxLastBits = 0x07 // bit 0..2: see above
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//controlRegReserved3to5 = 0x38
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controlRegTStartNowBit = 0x40 // bit 6: timer starts immediately, if 1; reading always returns logic 0
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controlRegTStopNow = 0x80 // bit 7: timer stops immediately, if 1; reading always returns logic 0
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)
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const (
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regBitFraming = 0x0D // adjustments for bit-oriented frames
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// ------------ values --------------------
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bitFramingRegReset = 0x00 // see table 47 of data sheet
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// used for transmission of bit oriented frames: defines the number of bits of the last byte that will be transmitted
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// 000b indicates that all bits of the last byte will be transmitted
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bitFramingRegTxLastBits = 0x07 // bit 0..2: see above
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//bitFramingRegReservedBit3 = 0x08
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// used for reception of bit-oriented frames: defines the bit position for the first bit received to be stored in the
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// FIFO buffer, example:
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// 0: LSB of the received bit is stored at bit position 0, the second received bit is stored at bit position 1
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// 1: LSB of the received bit is stored at bit position 1, the second received bit is stored at bit position 2
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// 7: LSB of the received bit is stored at bit position 7, the second received bit is stored in the next byte that
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// follows at bit position 0
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// These bits are only to be used for bitwise anticollision at 106 kBd, for all other modes they are set to 0
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bitFramingRegRxAlign = 0x70 // bit 4..6: see above
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//starts the transmission of data, only valid in combination with the Transceive command
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bitFramingRegStartSendBit = 0x80 // bit 7: see above
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)
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const (
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regColl = 0x0E // bit position of the first bit-collision detected on the RF interface
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// 4 to 0 CollPos[4:0]-
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// shows the bit position of the first detected collision in a received frame only data bits are interpreted example:
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// 00: indicates a bit-collision in the 32nd bit
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// 01: indicates a bit-collision in the 1st bit
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// 08: indicates a bit-collision in the 8th bit
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// These bits will only be interpreted if the CollPosNotValid bit is set to logic 0
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collRegCollPos = 0x1F // bit 0..4: read-only, see above
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// no collision detected or the position of the collision is out of the range of CollPos[4:0], if set to 1
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collRegCollPosNotValidBit = 0x20 // bit 5: read-only, see above
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//collRegReservedBit6 = 0x40
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// all received bits will be cleared after a collision only used during bitwise anticollision at 106 kBd, otherwise it
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// is set to logic 1
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collRegValuesAfterCollBit = 0x80 // bit 7: see above
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)
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// 0x0F // reserved for future use
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// Page 1: Command
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// 0x10 // reserved for future use
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const (
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regMode = 0x11 // defines general modes for transmitting and receiving
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// ------------ values --------------------
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modeRegReset = 0x3F // see table 55 of data sheet
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// bit 0..1: defines the preset value for the CRC coprocessor for the CalcCRC command; Remark: during any
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// communication, the preset values are selected automatically according to the definition of bits in the rxModeReg
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// and TxMode registers
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modeRegCRCPreset0000 = 0x00 // 0x0000
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modeRegCRCPreset6363 = 0x01 // 0x6363
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modeRegCRCPresetA671 = 0x10 // 0xA671
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modeRegCRCPresetFFFF = 0x11 // 0xFFFF
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//modeRegReservedBit2 = 0x04
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// defines the polarity of pin MFIN; Remark: the internal envelope signal is encoded active LOW, changing this bit
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// generates a MFinActIRq event
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modeRegPolMFinBit = 0x08 // bit 3: polarity of pin MFIN is active HIGH, is set to 1
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//modeRegReservedBit4 = 0x10
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modeRegTxWaitRFBit = 0x20 // bit 5: transmitter can only be started if an RF field is generated, if set to 1
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//modeRegReservedBit6 = 0x40
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// CRC coprocessor calculates the CRC with MSB first 0 in the CRCResult register the values for the CRCResultMSB[7:0]
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// bits and the CRCResultLSB[7:0] bits are bit reversed; Remark: during RF communication this bit is ignored
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modeRegMSBFirstBit = 0x80 // bit 7: see above, if set to 1
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)
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const (
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regTxMode = 0x12 // defines transmission data rate and framing
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regRxMode = 0x13 // defines reception data rate and framing
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// ------------ values --------------------
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rxtxModeRegReset = 0x00
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//txModeRegReserved = 0x07 // bit 0..2 reserved for TX
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//rxModeRegReserved = 0x03 // bit 0,1 reserved for RX
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// 0: receiver is deactivated after receiving a data frame
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// 1: able to receive more than one data frame; only valid for data rates above 106 kBd in order to handle the
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// polling command; after setting this bit the Receive and Transceive commands will not terminate automatically.
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// Multiple reception can only be deactivated by writing any command (except the Receive command) to the commandReg
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// register, or by the host clearing the bit if set to logic 1, an error byte is added to the FIFO buffer at the
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// end of a received data stream which is a copy of the Error register value. For the version 2.0 the
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// CRC status is reflected in the signal CRCOk, which indicates the actual status of the CRC coprocessor. For the
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// version 1.0 the CRC status is reflected in the signal CRCErr.
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rxModeRegRxMultipleBit = 0x04
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// an invalid received data stream (less than 4 bits received) will be ignored and the receiver remains active
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rxModeRegRxNoErrBit = 0x08 // bit 3
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txModeRegInvModBit = 0x08 // bit 3: modulation of transmitted data is inverted, if 1
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// bit 4..6: defines the bit rate during data transmission; the handles transfer speeds up to 848 kBd
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rxtxModeRegSpeed106kBd = 0x00 //106 kBd
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rxtxModeRegSpeed212kBd = 0x10 //212 kBd
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rxtxModeRegSpeed424kBd = 0x20 //424 kBd
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rxtxModeRegSpeed848kBd = 0x30 //848 kBd
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rxtxModeRegSpeedRes1 = 0x40 //reserved
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rxtxModeRegSpeedRes2 = 0x50 //reserved
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rxtxModeRegSpeedRes3 = 0x60 //reserved
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rxtxModeRegSpeedRes4 = 0x70 //reserved
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// RX: enables the CRC calculation during reception
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// TX: enables CRC generation during data transmission
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rxtxModeRegTxCRCEnBit = 0x80 // bit 7: can only be set to logic 0 at 106 kBd
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)
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const (
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regTxControl = 0x14 // controls the logical behavior of the antenna driver pins TX1 and TX2
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// ------------ values --------------------
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regtxControlRegReset = 0x80 // see table 61 of data sheet
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// signal on pin TX1 delivers the 13.56 MHz energy carrier modulated by the transmission data
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txControlRegTx1RFEn1outputBit = 0x01 // bit 0: see above
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// signal on pin TX2 delivers the 13.56 MHz energy carrier modulated by the transmission data
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txControlRegTx2RFEn1outputBit = 0x02 // bit 1: see above
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//txControlRegReservedBit2 = 0x04
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// signal on pin TX2 continuously delivers the unmodulated 13.56 MHz energy carrier0Tx2CW bit is enabled to modulate
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// the 13.56 MHz energy carrier
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txControlRegTx2CW1outputBit = 0x08 // bit 3: see above
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txControlRegInvTx1RFOffBit = 0x10 // bit 4: output signal on pin TX1 inverted if driver TX1 is disabled, if 1
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txControlRegInvTx2RFOffBit = 0x20 // bit 5: output signal on pin TX2 inverted if driver TX2 is disabled, if 1
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txControlRegInvTx1RFOnBit = 0x40 // bit 6: output signal on pin TX1 inverted if driver TX1 is enabled, if 1
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txControlRegInvTx2RFOnBit = 0x80 // bit 7: output signal on pin TX2 inverted if driver TX2 is enabled, if 1
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)
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const (
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regTxASK = 0x15 // controls the setting of the transmission modulation
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// ------------ values --------------------
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txASKRegReset = 0x00 // see table 63 of data sheet
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//txASKRegReserved = 0x3F // bit 0..5
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txASKRegForce100ASKBit = 0x40 // bit 6: forces a 100 % ASK modulation independent of the ModGsP register
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//txASKRegReservedBit7 = 0x80
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)
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const (
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regTxSel = 0x16 // selects the internal sources for the antenna driver
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regRxSel = 0x17 // selects internal receiver settings
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regRxThreshold = 0x18 // selects thresholds for the bit decoder
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regDemod = 0x19 // defines demodulator settings
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// 0x1A // reserved for future use
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// 0x1B // reserved for future use
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regMfTx = 0x1C // controls some MIFARE communication transmit parameters
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regMfRx = 0x1D // controls some MIFARE communication receive parameters
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// 0x1E // reserved for future use
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regSerialSpeed = 0x1F // selects the speed of the serial UART interface
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// Page 2: Configuration
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// 0x20 // reserved for future use
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regCRCResultH = 0x21 // shows the MSB and LSB values of the CRC calculation
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regCRCResultL = 0x22
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// 0x23 // reserved for future use
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)
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const (
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regModWidth = 0x24
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// ------------ values --------------------
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modWidthRegReset = 0x26 // see table 93 of data sheet
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)
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// 0x25 // reserved for future use
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const (
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regRFCfg = 0x26 // configures the receiver gain
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// ------------ values --------------------
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rfcCfgRegReset = 0x48 // see table 97 of data sheet
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//rfcCfgRegReserved03 = 0x07
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// bit 4..6: defines the receiver’s signal voltage gain factor
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rfcCfgRegRxGain18dB = 0x00
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rfcCfgRegRxGain23dB = 0x10
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rfcCfgRegRxGain018dB = 0x20
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rfcCfgRegRxGain023dB = 0x30
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rfcCfgRegRxGain33dB = 0x40
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rfcCfgRegRxGain38dB = 0x50
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rfcCfgRegRxGain43dB = 0x60
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rfcCfgRegRxGain48dB = 0x70
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//rfcCfgRegReserved7 = 0x80
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)
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const (
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// ------------ unused commands --------------------
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regGsN = 0x27 // selects the conductance of the antenna driver pins TX1 and TX2 for modulation
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regCWGsP = 0x28 // defines the conductance of the p-driver output during periods of no modulation
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regModGsP = 0x29 // defines the conductance of the p-driver output during periods of modulation
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)
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const (
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regTMode = 0x2A // defines settings for the internal timer
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regTPrescaler = 0x2B // the lower 8 bits of the TPrescaler value. The 4 high bits are in tModeReg.
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// ------------ values --------------------
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tModeRegReset = 0x00 // see table 105 of data sheet
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tPrescalerRegReset = 0x00 // see table 107 of data sheet
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// timer starts automatically at the end of the transmission in all communication modes at all speeds; if the
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// RxMode register’s RxMultiple bit is not set, the timer stops immediately after receiving the 5th bit (1 start
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// bit, 4 data bits); if the RxMultiple bit is set to logic 1 the timer never stops, in which case the timer can be
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// stopped by setting the Control register’s TStopNow bit to logic 1
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tModeRegTAutoBit = 0x80 // bit 7: see above
|
||
// bit 6,5: indicates that the timer is not influenced by the protocol; internal timer is running in
|
||
// gated mode; Remark: in gated mode, the Status1 register’s TRunning bit is logic 1 when the timer is enabled by
|
||
// the TMode register’s TGated bits; this bit does not influence the gating signal
|
||
tModeRegTGatedNon = 0x00 // non-gated mode
|
||
tModeRegTGatedMFIN = 0x20 // gated by pin MFIN
|
||
tModeRegTGatedAUX1 = 0x40 // gated by pin AUX1
|
||
// 1: timer automatically restarts its count-down from the 16-bit timer reload value instead of counting down to zero
|
||
// 0: timer decrements to 0 and the ComIrq register’s TimerIRq bit is set to logic 1
|
||
tModeRegTAutoRestartBit = 0x10 // bit 4, see above
|
||
// defines the higher 4 bits of the TPrescaler value; The following formula is used to calculate the timer
|
||
// frequency if the Demod register’s TPrescalEven bit in Demot register’s set to logic 0:
|
||
// ftimer = 13.56 MHz / (2*TPreScaler+1); TPreScaler = [tPrescalerRegHi:tPrescalerRegLo]
|
||
// TPrescaler value on 12 bits) (Default TPrescalEven bit is logic 0)
|
||
// The following formula is used to calculate the timer frequency if the Demod register’s TPrescalEven bit is set
|
||
// to logic 1: ftimer = 13.56 MHz / (2*TPreScaler+2).
|
||
tModeRegtPrescalerRegValue25us = 0x0A9 // 169 => fRegtimer=40kHz, timer period of 25μs.
|
||
tModeRegtPrescalerRegValue38us = 0x0FF // 255 => fRegtimer=26kHz, timer period of 38μs.
|
||
tModeRegtPrescalerRegValue500us = 0xD3E // 3390 => fRegtimer= 2kHz, timer period of 500us.
|
||
tModeRegtPrescalerRegValue604us = 0xFFF // 4095 => fRegtimer=1.65kHz, timer period of 604us.
|
||
)
|
||
|
||
const (
|
||
// defines the 16-bit timer reload value; on a start event, the timer loads the timer reload value changing this
|
||
// register affects the timer only at the next start event
|
||
regTReloadH = 0x2C
|
||
regTReloadL = 0x2D
|
||
// ------------ values --------------------
|
||
tReloadRegReset = 0x0000 // see table 109, 111
|
||
tReloadRegValue25ms = 0x03E8 // 1000, 25ms before timeout
|
||
tReloadRegValue833ms = 0x001E // 30, 833ms before timeout
|
||
)
|
||
|
||
const (
|
||
// ------------ unused commands --------------------
|
||
regTCounterValueH = 0x2E // shows the 16-bit timer value
|
||
regTCounterValueL = 0x2F
|
||
|
||
// Page 3: Test Registers
|
||
// 0x30 // reserved for future use
|
||
regTestSel1 = 0x31 // general test signal configuration
|
||
regTestSel2 = 0x32 // general test signal configuration
|
||
regTestPinEn = 0x33 // enables pin output driver on pins D1 to D7
|
||
regTestPinValue = 0x34 // defines the values for D1 to D7 when it is used as an I/O bus
|
||
regTestBus = 0x35 // shows the status of the internal test bus
|
||
regAutoTest = 0x36 // controls the digital self-test
|
||
regVersion = 0x37 // shows the software version
|
||
regAnalogTest = 0x38 // controls the pins AUX1 and AUX2
|
||
regTestDAC1 = 0x39 // defines the test value for TestDAC1
|
||
regTestDAC2 = 0x3A // defines the test value for TestDAC2
|
||
regTestADC = 0x3B // shows the value of ADC I and Q channels
|
||
// 0x3C // reserved for production tests
|
||
// 0x3D // reserved for production tests
|
||
// 0x3E // reserved for production tests
|
||
// 0x3F // reserved for production tests
|
||
)
|